[llvm] [RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (PR #89174)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 08:14:08 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/89174
>From f2f5728c4335834384fb52916f08fc942a19e307 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 17 Apr 2024 23:41:23 -0700
Subject: [PATCH] [RISCV] Rename FeatureRVE to FeatureStdExtE. NFC
Planning to declare all extensions in tablegen so we can generate
the tables for RISCVISAInfo.cpp. This requires making "e" consistent
with other extensions.
---
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
.../Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 +-
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 12 ++++++------
6 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 455a90269d0258..d926ccdb59e19b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -83,7 +83,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
- bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureRVE); }
+ bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); }
RISCVTargetStreamer &getTargetStreamer() {
assert(getParser().getStreamer().getTargetStreamer() &&
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 6aadabdf1bc61a..998b9181efe6ac 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -64,7 +64,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
- bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
+ bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
if (RegNo >= 32 || (IsRVE && RegNo >= 16))
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 5d9a58babe606c..67c9060b515772 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -40,7 +40,7 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
StringRef ABIName) {
auto TargetABI = getTargetABI(ABIName);
bool IsRV64 = TT.isArch64Bit();
- bool IsRVE = FeatureBits[RISCV::FeatureRVE];
+ bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];
if (!ABIName.empty() && TargetABI == ABI_Unknown) {
errs()
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 8c434a23b10ee7..631fd449580143 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -16,6 +16,10 @@ def FeatureStdExtI
: SubtargetFeature<"i", "HasStdExtI", "true",
"'I' (Base Integer Instruction Set)">;
+def FeatureStdExtE
+ : SubtargetFeature<"e", "HasStdExtE", "true",
+ "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
+
def FeatureStdExtZic64b
: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
"'Zic64b' (Cache Block Size Is 64 Bytes)">;
@@ -1165,10 +1169,6 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
defvar RV32 = DefaultMode;
def RV64 : HwMode<"+64bit", [IsRV64]>;
-def FeatureRVE
- : SubtargetFeature<"e", "IsRVE", "true",
- "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
-
def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b0deb1d2669952..82339dd2072172 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18951,7 +18951,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
case CallingConv::RISCV_VectorCall:
break;
case CallingConv::GHC:
- if (Subtarget.isRVE())
+ if (Subtarget.hasStdExtE())
report_fatal_error("GHC calling convention is not supported on RVE!");
if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
@@ -19189,7 +19189,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
if (CallConv == CallingConv::GHC) {
- if (Subtarget.isRVE())
+ if (Subtarget.hasStdExtE())
report_fatal_error("GHC calling convention is not supported on RVE!");
ArgCCInfo.AnalyzeCallOperands(Outs, RISCV::CC_RISCV_GHC);
} else
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 367a62e830cbf5..6a48848e202201 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -65,10 +65,10 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
if (Subtarget.hasStdExtD())
return CSR_XLEN_F64_Interrupt_SaveList;
if (Subtarget.hasStdExtF())
- return Subtarget.isRVE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
- : CSR_XLEN_F32_Interrupt_SaveList;
- return Subtarget.isRVE() ? CSR_Interrupt_RVE_SaveList
- : CSR_Interrupt_SaveList;
+ return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
+ : CSR_XLEN_F32_Interrupt_SaveList;
+ return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
+ : CSR_Interrupt_SaveList;
}
bool HasVectorCSR =
@@ -126,7 +126,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
// There are only 16 GPRs for RVE.
- if (Subtarget.isRVE())
+ if (Subtarget.hasStdExtE())
for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
markSuperRegs(Reserved, Reg);
@@ -145,7 +145,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, RISCV::VCIX_STATE);
if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
- if (Subtarget.isRVE())
+ if (Subtarget.hasStdExtE())
report_fatal_error("Graal reserved registers do not exist in RVE");
markSuperRegs(Reserved, RISCV::X23);
markSuperRegs(Reserved, RISCV::X27);
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