[llvm] AMDGPU: Implement llvm.set.rounding (PR #88587)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 06:55:03 PDT 2024
================
@@ -0,0 +1,1919 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX678,GFX6 %s
+; RUN: llc -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX678,GFX7 %s
+; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX678,GFX8 %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11 %s
+
+declare void @llvm.set.rounding(i32)
+declare i32 @llvm.get.rounding()
+
+define amdgpu_gfx void @s_set_rounding(i32 inreg %rounding) {
+; GFX678-LABEL: s_set_rounding:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_add_i32 s34, s4, -4
+; GFX678-NEXT: s_cmp_lt_u32 s4, 4
+; GFX678-NEXT: s_cselect_b32 s34, s4, s34
+; GFX678-NEXT: s_lshl_b32 s36, s34, 2
+; GFX678-NEXT: s_mov_b32 s34, 0x1c84a50f
+; GFX678-NEXT: s_mov_b32 s35, 0xb73e62d9
+; GFX678-NEXT: s_lshr_b64 s[34:35], s[34:35], s36
+; GFX678-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: s_set_rounding:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_add_i32 s34, s4, -4
+; GFX9-NEXT: s_cmp_lt_u32 s4, 4
+; GFX9-NEXT: s_cselect_b32 s34, s4, s34
+; GFX9-NEXT: s_lshl_b32 s36, s34, 2
+; GFX9-NEXT: s_mov_b32 s34, 0x1c84a50f
+; GFX9-NEXT: s_mov_b32 s35, 0xb73e62d9
+; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], s36
+; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: s_set_rounding:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_add_i32 s34, s4, -4
+; GFX10-NEXT: s_cmp_lt_u32 s4, 4
+; GFX10-NEXT: s_cselect_b32 s34, s4, s34
+; GFX10-NEXT: s_lshl_b32 s36, s34, 2
+; GFX10-NEXT: s_mov_b32 s34, 0x1c84a50f
+; GFX10-NEXT: s_mov_b32 s35, 0xb73e62d9
+; GFX10-NEXT: s_lshr_b64 s[34:35], s[34:35], s36
+; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s34
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: s_set_rounding:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s0, s4, -4
+; GFX11-NEXT: s_cmp_lt_u32 s4, 4
+; GFX11-NEXT: s_cselect_b32 s0, s4, s0
+; GFX11-NEXT: s_lshl_b32 s2, s0, 2
+; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ call void @llvm.set.rounding(i32 %rounding)
+ ret void
+}
+
+define amdgpu_kernel void @s_set_rounding_kernel(i32 inreg %rounding) {
+; GFX6-LABEL: s_set_rounding_kernel:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s2, s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX6-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX6-NEXT: ;;#ASMSTART
+; GFX6-NEXT: ;;#ASMEND
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_add_i32 s3, s2, -4
+; GFX6-NEXT: s_cmp_lt_u32 s2, 4
+; GFX6-NEXT: s_cselect_b32 s2, s2, s3
+; GFX6-NEXT: s_lshl_b32 s2, s2, 2
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_set_rounding_kernel:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_load_dword s2, s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX7-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX7-NEXT: ;;#ASMSTART
+; GFX7-NEXT: ;;#ASMEND
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_add_i32 s3, s2, -4
+; GFX7-NEXT: s_cmp_lt_u32 s2, 4
+; GFX7-NEXT: s_cselect_b32 s2, s2, s3
+; GFX7-NEXT: s_lshl_b32 s2, s2, 2
+; GFX7-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_set_rounding_kernel:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dword s2, s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX8-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX8-NEXT: ;;#ASMSTART
+; GFX8-NEXT: ;;#ASMEND
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_add_i32 s3, s2, -4
+; GFX8-NEXT: s_cmp_lt_u32 s2, 4
+; GFX8-NEXT: s_cselect_b32 s2, s2, s3
+; GFX8-NEXT: s_lshl_b32 s2, s2, 2
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX8-NEXT: s_endpgm
+;
+; GFX9-LABEL: s_set_rounding_kernel:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x24
+; GFX9-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX9-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_add_i32 s3, s2, -4
+; GFX9-NEXT: s_cmp_lt_u32 s2, 4
+; GFX9-NEXT: s_cselect_b32 s2, s2, s3
+; GFX9-NEXT: s_lshl_b32 s2, s2, 2
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX9-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_set_rounding_kernel:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
+; GFX10-NEXT: ;;#ASMSTART
+; GFX10-NEXT: ;;#ASMEND
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_add_i32 s1, s0, -4
+; GFX10-NEXT: s_cmp_lt_u32 s0, 4
+; GFX10-NEXT: s_cselect_b32 s2, s0, s1
+; GFX10-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX10-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX10-NEXT: s_lshl_b32 s2, s2, 2
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_set_rounding_kernel:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ;;#ASMEND
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_i32 s1, s0, -4
+; GFX11-NEXT: s_cmp_lt_u32 s0, 4
+; GFX11-NEXT: s_cselect_b32 s2, s0, s1
+; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX11-NEXT: s_lshl_b32 s2, s2, 2
+; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
+; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0
+; GFX11-NEXT: s_endpgm
+ call void @llvm.set.rounding(i32 %rounding)
+ call void asm sideeffect "",""()
+ ret void
+}
+
+define void @v_set_rounding(i32 %rounding) {
+; GFX6-LABEL: v_set_rounding:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, -4, v0
+; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 4, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX6-NEXT: s_mov_b32 s4, 0x1c84a50f
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX6-NEXT: s_mov_b32 s5, 0xb73e62d9
+; GFX6-NEXT: v_lshr_b64 v[0:1], s[4:5], v0
+; GFX6-NEXT: v_readfirstlane_b32 s4, v0
+; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_set_rounding:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_add_i32_e32 v1, vcc, -4, v0
+; GFX7-NEXT: v_cmp_gt_u32_e32 vcc, 4, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX7-NEXT: s_mov_b32 s4, 0x1c84a50f
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX7-NEXT: s_mov_b32 s5, 0xb73e62d9
+; GFX7-NEXT: v_lshr_b64 v[0:1], s[4:5], v0
+; GFX7-NEXT: v_readfirstlane_b32 s4, v0
+; GFX7-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_set_rounding:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, -4, v0
+; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 4, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX8-NEXT: s_mov_b32 s4, 0x1c84a50f
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX8-NEXT: s_mov_b32 s5, 0xb73e62d9
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[4:5]
+; GFX8-NEXT: v_readfirstlane_b32 s4, v0
+; GFX8-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_set_rounding:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v1, -4, v0
+; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 4, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x1c84a50f
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: s_mov_b32 s5, 0xb73e62d9
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[4:5]
+; GFX9-NEXT: v_readfirstlane_b32 s4, v0
+; GFX9-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_set_rounding:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_add_nc_u32_e32 v1, -4, v0
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 4, v0
+; GFX10-NEXT: s_mov_b32 s4, 0x1c84a50f
+; GFX10-NEXT: s_mov_b32 s5, 0xb73e62d9
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[4:5]
+; GFX10-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s4
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_set_rounding:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u32_e32 v1, -4, v0
+; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 4, v0
+; GFX11-NEXT: s_mov_b32 s0, 0x1c84a50f
+; GFX11-NEXT: s_mov_b32 s1, 0xb73e62d9
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
----------------
jayfoad wrote:
It would be nice if this could use alignbit, since only the low half of the result is used.
https://github.com/llvm/llvm-project/pull/88587
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