[llvm] [WIP] Introduce address sanitizer instrumentation for LDS lowered by amdgpu-sw-lower-lds pass (PR #89208)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 03:48:50 PDT 2024
https://github.com/skc7 created https://github.com/llvm/llvm-project/pull/89208
This is WIP PR for instrumenting "LDS accesses lowered by amdgpu-sw-lower-lds".
- For every kernel, "llvm.amdgcn.sw.lds.<kernel-name>.md" initializer would be updated to add information regarding redzone size and redzone offset.
- Every member in the metaddata struct type will now have four fields. {GV.StartOffset, (aligned GV+redzone size), Redzone.StartOffset, Redzone.size}.
- A call to "__asan_poison_region" would be made for every redzone corresponding to static LDS.
>From 7ccf4f94ca1f95bc01859621eaf5b4dab0a24c25 Mon Sep 17 00:00:00 2001
From: skc7 <Krishna.Sankisa at amd.com>
Date: Fri, 8 Mar 2024 16:43:57 +0530
Subject: [PATCH 1/2] [WIP] Enable asan LDS instrumentation
---
.../Instrumentation/AddressSanitizer.cpp | 237 +++++-
.../asan-instr-lds-dynamic-indirect-access.ll | 441 ++++++++++
.../AMDGPU/asan-instr-lds-dynamic-lds-test.ll | 199 +++++
...ds-multi-static-dynamic-indirect-access.ll | 787 ++++++++++++++++++
...nstr-lds-static-dynamic-indirect-access.ll | 441 ++++++++++
.../asan-instr-lds-static-indirect-access.ll | 400 +++++++++
.../asan-instr-static-dynamic-lds-test.ll | 262 ++++++
.../AMDGPU/asan-instr-static-lds-test.ll | 177 ++++
8 files changed, 2904 insertions(+), 40 deletions(-)
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-lds-test.ll
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll
create mode 100755 llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll
diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index 26fedbfd65dd410..6067b996c42d6ba 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -628,12 +628,6 @@ ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel,
} // namespace llvm
-static uint64_t getRedzoneSizeForScale(int MappingScale) {
- // Redzone used for stack and globals is at least 32 bytes.
- // For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively.
- return std::max(32U, 1U << MappingScale);
-}
-
static uint64_t GetCtorAndDtorPriority(Triple &TargetTriple) {
if (TargetTriple.isOSEmscripten()) {
return kAsanEmscriptenCtorAndDtorPriority;
@@ -939,10 +933,7 @@ class ModuleAddressSanitizer {
StringRef getGlobalMetadataSection() const;
void poisonOneInitializer(Function &GlobalInit, GlobalValue *ModuleName);
void createInitializerPoisonCalls(Module &M, GlobalValue *ModuleName);
- uint64_t getMinRedzoneSizeForGlobal() const {
- return getRedzoneSizeForScale(Mapping.Scale);
- }
- uint64_t getRedzoneSizeForGlobal(uint64_t SizeInBytes) const;
+
int GetAsanVersion(const Module &M) const;
bool CompileKernel;
@@ -1239,6 +1230,178 @@ void AddressSanitizerPass::printPipeline(
OS << '>';
}
+static uint64_t getRedzoneSizeForScale(int MappingScale) {
+ // Redzone used for stack and globals is at least 32 bytes.
+ // For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively.
+ return std::max(32U, 1U << MappingScale);
+}
+
+static uint64_t getMinRedzoneSizeForGlobal(int Scale) {
+ return getRedzoneSizeForScale(Scale);
+}
+
+static uint64_t getRedzoneSizeForGlobal(int Scale, uint64_t SizeInBytes) {
+ constexpr uint64_t kMaxRZ = 1 << 18;
+ const uint64_t MinRZ = getMinRedzoneSizeForGlobal(Scale);
+
+ uint64_t RZ = 0;
+ if (SizeInBytes <= MinRZ / 2) {
+ // Reduce redzone size for small size objects, e.g. int, char[1]. MinRZ is
+ // at least 32 bytes, optimize when SizeInBytes is less than or equal to
+ // half of MinRZ.
+ RZ = MinRZ - SizeInBytes;
+ } else {
+ // Calculate RZ, where MinRZ <= RZ <= MaxRZ, and RZ ~ 1/4 * SizeInBytes.
+ RZ = std::clamp((SizeInBytes / MinRZ / 4) * MinRZ, MinRZ, kMaxRZ);
+
+ // Round up to multiple of MinRZ.
+ if (SizeInBytes % MinRZ)
+ RZ += MinRZ - (SizeInBytes % MinRZ);
+ }
+
+ assert((RZ + SizeInBytes) % MinRZ == 0);
+
+ return RZ;
+}
+
+static GlobalVariable *getKernelSwLDSGlobal(Module &M, Function &F) {
+ SmallString<64> KernelLDSName("llvm.amdgcn.sw.lds.");
+ KernelLDSName += F.getName();
+ return M.getNamedGlobal(KernelLDSName);
+}
+
+static GlobalVariable *getKernelSwLDSMetadataGlobal(Module &M, Function &F) {
+ SmallString<64> KernelLDSName("llvm.amdgcn.sw.lds.");
+ KernelLDSName += F.getName();
+ KernelLDSName += ".md";
+ return M.getNamedGlobal(KernelLDSName);
+}
+
+static void UpdateSwLDSMetadataWithRedzoneInfo(Function &F, int Scale) {
+ Module *M = F.getParent();
+ GlobalVariable *SwLDSMetadataGlobal = getKernelSwLDSMetadataGlobal(*M, F);
+ GlobalVariable *SwLDSGlobal = getKernelSwLDSGlobal(*M, F);
+ if (!SwLDSMetadataGlobal || !SwLDSGlobal)
+ return;
+
+ LLVMContext &Ctx = M->getContext();
+ Type *Int32Ty = Type::getInt32Ty(Ctx);
+
+ Constant *MdInit = SwLDSMetadataGlobal->getInitializer();
+ Align MdAlign = Align(SwLDSMetadataGlobal->getAlign().valueOrOne());
+ Align LDSAlign = Align(SwLDSGlobal->getAlign().valueOrOne());
+
+ StructType *MDStructType =
+ cast<StructType>(SwLDSMetadataGlobal->getValueType());
+ assert(MDStructType);
+ unsigned NumStructs = MDStructType->getNumElements();
+
+ std::vector<Type *> Items;
+ std::vector<Constant *> Initializers;
+ uint32_t MallocSize = 0;
+ //{GV.start, Align(GV.size + Redzone.size), Redzone.start, Redzone.size}
+ StructType *LDSItemTy =
+ StructType::create(Ctx, {Int32Ty, Int32Ty, Int32Ty, Int32Ty}, "");
+ for (unsigned i = 0; i < NumStructs; i++) {
+ Items.push_back(LDSItemTy);
+ ConstantStruct *member =
+ dyn_cast<ConstantStruct>(MdInit->getAggregateElement(i));
+ Constant *NewInitItem;
+ if (member) {
+ ConstantInt *GlobalSize =
+ cast<ConstantInt>(member->getAggregateElement(1U));
+ unsigned GlobalSizeValue = GlobalSize->getZExtValue();
+ Constant *NewItemStartOffset = ConstantInt::get(Int32Ty, MallocSize);
+ if (GlobalSizeValue) {
+ const uint64_t RightRedzoneSize =
+ getRedzoneSizeForGlobal(Scale, GlobalSizeValue);
+ MallocSize += GlobalSizeValue;
+ Constant *NewItemRedzoneStartOffset =
+ ConstantInt::get(Int32Ty, MallocSize);
+ MallocSize += RightRedzoneSize;
+ Constant *NewItemRedzoneSize =
+ ConstantInt::get(Int32Ty, RightRedzoneSize);
+
+ unsigned NewItemAlignGlobalPlusRedzoneSize =
+ alignTo(GlobalSizeValue + RightRedzoneSize, LDSAlign);
+ Constant *NewItemAlignGlobalPlusRedzoneSizeConst =
+ ConstantInt::get(Int32Ty, NewItemAlignGlobalPlusRedzoneSize);
+ NewInitItem = ConstantStruct::get(
+ LDSItemTy,
+ {NewItemStartOffset, NewItemAlignGlobalPlusRedzoneSizeConst,
+ NewItemRedzoneStartOffset, NewItemRedzoneSize});
+ MallocSize = alignTo(MallocSize, LDSAlign);
+ } else {
+ Constant *CurrMallocSize = ConstantInt::get(Int32Ty, MallocSize);
+ Constant *zero = ConstantInt::get(Int32Ty, 0);
+ NewInitItem =
+ ConstantStruct::get(LDSItemTy, {CurrMallocSize, zero, zero, zero});
+ }
+ } else {
+ Constant *CurrMallocSize = ConstantInt::get(Int32Ty, MallocSize);
+ Constant *zero = ConstantInt::get(Int32Ty, 0);
+ NewInitItem =
+ ConstantStruct::get(LDSItemTy, {CurrMallocSize, zero, zero, zero});
+ }
+ Initializers.push_back(NewInitItem);
+ }
+
+ StructType *MetadataStructType = StructType::create(Ctx, Items, "");
+
+ GlobalVariable *NewSwLDSMetadataGlobal = new GlobalVariable(
+ *M, MetadataStructType, false, GlobalValue::InternalLinkage,
+ PoisonValue::get(MetadataStructType), "", nullptr,
+ GlobalValue::NotThreadLocal, 1, false);
+ Constant *Data = ConstantStruct::get(MetadataStructType, Initializers);
+ NewSwLDSMetadataGlobal->setInitializer(Data);
+ NewSwLDSMetadataGlobal->setAlignment(MdAlign);
+ GlobalValue::SanitizerMetadata MD;
+ MD.NoAddress = true;
+ NewSwLDSMetadataGlobal->setSanitizerMetadata(MD);
+
+ for (Use &U : make_early_inc_range(SwLDSMetadataGlobal->uses())) {
+ if (GEPOperator *GEP = dyn_cast<GEPOperator>(U.getUser())) {
+ SmallVector<Constant *> Indices;
+ for (Use &Idx : GEP->indices()) {
+ Indices.push_back(cast<Constant>(Idx));
+ }
+ Constant *NewGEP = ConstantExpr::getGetElementPtr(
+ MetadataStructType, NewSwLDSMetadataGlobal, Indices, true);
+ GEP->replaceAllUsesWith(NewGEP);
+ }
+ if (LoadInst *Load = dyn_cast<LoadInst>(U.getUser())) {
+ Constant *zero = ConstantInt::get(Int32Ty, 0);
+ SmallVector<Constant *> Indices{zero, zero, zero};
+ Constant *NewGEP = ConstantExpr::getGetElementPtr(
+ MetadataStructType, NewSwLDSMetadataGlobal, Indices, true);
+ IRBuilder<> IRB(Load);
+ LoadInst *NewLoad = IRB.CreateLoad(Load->getType(), NewGEP);
+ Load->replaceAllUsesWith(NewLoad);
+ Load->eraseFromParent();
+ }
+ if (StoreInst *Store = dyn_cast<StoreInst>(U.getUser())) {
+ Constant *zero = ConstantInt::get(Int32Ty, 0);
+ SmallVector<Constant *> Indices{zero, zero, zero};
+ Constant *NewGEP = ConstantExpr::getGetElementPtr(
+ MetadataStructType, NewSwLDSMetadataGlobal, Indices, true);
+ IRBuilder<> IRB(Store);
+ StoreInst *NewStore = IRB.CreateStore(Store->getValueOperand(), NewGEP);
+ Store->replaceAllUsesWith(NewStore);
+ Store->eraseFromParent();
+ }
+ }
+ SwLDSMetadataGlobal->replaceAllUsesWith(NewSwLDSMetadataGlobal);
+ NewSwLDSMetadataGlobal->takeName(SwLDSMetadataGlobal);
+ SwLDSMetadataGlobal->eraseFromParent();
+ return;
+}
+
+static void preProcessAMDGPULDSAccesses(Module &M, int Scale) {
+ for (Function &F : M)
+ UpdateSwLDSMetadataWithRedzoneInfo(F, Scale);
+ return;
+}
+
AddressSanitizerPass::AddressSanitizerPass(
const AddressSanitizerOptions &Options, bool UseGlobalGC,
bool UseOdrIndicator, AsanDtorKind DestructorKind,
@@ -1249,6 +1412,13 @@ AddressSanitizerPass::AddressSanitizerPass(
PreservedAnalyses AddressSanitizerPass::run(Module &M,
ModuleAnalysisManager &MAM) {
+ Triple TargetTriple = Triple(M.getTargetTriple());
+
+ if (TargetTriple.isAMDGPU()) {
+ unsigned LongSize = M.getDataLayout().getPointerSizeInBits();
+ ShadowMapping Mapping = getShadowMapping(TargetTriple, LongSize, false);
+ preProcessAMDGPULDSAccesses(M, Mapping.Scale);
+ }
ModuleAddressSanitizer ModuleSanitizer(
M, Options.InsertVersionCheck, Options.CompileKernel, Options.Recover,
UseGlobalGC, UseOdrIndicator, DestructorKind, ConstructorKind);
@@ -1304,7 +1474,15 @@ static bool GlobalWasGeneratedByCompiler(GlobalVariable *G) {
static bool isUnsupportedAMDGPUAddrspace(Value *Addr) {
Type *PtrTy = cast<PointerType>(Addr->getType()->getScalarType());
unsigned int AddrSpace = PtrTy->getPointerAddressSpace();
- if (AddrSpace == 3 || AddrSpace == 5)
+ if (AddrSpace == 5)
+ return true;
+ return false;
+}
+
+static bool isGlobalInAMDGPULdsAddrspace(Value *Addr) {
+ Type *PtrTy = cast<PointerType>(Addr->getType()->getScalarType());
+ unsigned int AddrSpace = PtrTy->getPointerAddressSpace();
+ if (AddrSpace == 3)
return true;
return false;
}
@@ -2021,7 +2199,8 @@ bool ModuleAddressSanitizer::shouldInstrumentGlobal(GlobalVariable *G) const {
if (!G->hasInitializer()) return false;
// Globals in address space 1 and 4 are supported for AMDGPU.
if (G->getAddressSpace() &&
- !(TargetTriple.isAMDGPU() && !isUnsupportedAMDGPUAddrspace(G)))
+ (!(TargetTriple.isAMDGPU() && !isUnsupportedAMDGPUAddrspace(G)) ||
+ !(TargetTriple.isAMDGPU() && !isGlobalInAMDGPULdsAddrspace(G))))
return false;
if (GlobalWasGeneratedByCompiler(G)) return false; // Our own globals.
// Two problems with thread-locals:
@@ -2029,7 +2208,9 @@ bool ModuleAddressSanitizer::shouldInstrumentGlobal(GlobalVariable *G) const {
// - Need to poison all copies, not just the main thread's one.
if (G->isThreadLocal()) return false;
// For now, just ignore this Global if the alignment is large.
- if (G->getAlign() && *G->getAlign() > getMinRedzoneSizeForGlobal()) return false;
+ if (G->getAlign() &&
+ *G->getAlign() > getMinRedzoneSizeForGlobal(Mapping.Scale))
+ return false;
// For non-COFF targets, only instrument globals known to be defined by this
// TU.
@@ -2552,7 +2733,8 @@ void ModuleAddressSanitizer::instrumentGlobals(IRBuilder<> &IRB, Module &M,
Type *Ty = G->getValueType();
const uint64_t SizeInBytes = DL.getTypeAllocSize(Ty);
- const uint64_t RightRedzoneSize = getRedzoneSizeForGlobal(SizeInBytes);
+ const uint64_t RightRedzoneSize =
+ getRedzoneSizeForGlobal(Mapping.Scale, SizeInBytes);
Type *RightRedZoneTy = ArrayType::get(IRB.getInt8Ty(), RightRedzoneSize);
StructType *NewTy = StructType::get(Ty, RightRedZoneTy);
@@ -2568,7 +2750,7 @@ void ModuleAddressSanitizer::instrumentGlobals(IRBuilder<> &IRB, Module &M,
G->getThreadLocalMode(), G->getAddressSpace());
NewGlobal->copyAttributesFrom(G);
NewGlobal->setComdat(G->getComdat());
- NewGlobal->setAlignment(Align(getMinRedzoneSizeForGlobal()));
+ NewGlobal->setAlignment(Align(getMinRedzoneSizeForGlobal(Mapping.Scale)));
// Don't fold globals with redzones. ODR violation detector and redzone
// poisoning implicitly creates a dependence on the global's address, so it
// is no longer valid for it to be marked unnamed_addr.
@@ -2688,31 +2870,6 @@ void ModuleAddressSanitizer::instrumentGlobals(IRBuilder<> &IRB, Module &M,
LLVM_DEBUG(dbgs() << M);
}
-uint64_t
-ModuleAddressSanitizer::getRedzoneSizeForGlobal(uint64_t SizeInBytes) const {
- constexpr uint64_t kMaxRZ = 1 << 18;
- const uint64_t MinRZ = getMinRedzoneSizeForGlobal();
-
- uint64_t RZ = 0;
- if (SizeInBytes <= MinRZ / 2) {
- // Reduce redzone size for small size objects, e.g. int, char[1]. MinRZ is
- // at least 32 bytes, optimize when SizeInBytes is less than or equal to
- // half of MinRZ.
- RZ = MinRZ - SizeInBytes;
- } else {
- // Calculate RZ, where MinRZ <= RZ <= MaxRZ, and RZ ~ 1/4 * SizeInBytes.
- RZ = std::clamp((SizeInBytes / MinRZ / 4) * MinRZ, MinRZ, kMaxRZ);
-
- // Round up to multiple of MinRZ.
- if (SizeInBytes % MinRZ)
- RZ += MinRZ - (SizeInBytes % MinRZ);
- }
-
- assert((RZ + SizeInBytes) % MinRZ == 0);
-
- return RZ;
-}
-
int ModuleAddressSanitizer::GetAsanVersion(const Module &M) const {
int LongSize = M.getDataLayout().getPointerSizeInBits();
bool isAndroid = Triple(M.getTargetTriple()).isAndroid();
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll
new file mode 100755
index 000000000000000..31dc4da9a9d6bd8
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll
@@ -0,0 +1,441 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 0 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 0 } }, no_sanitize_address
+ at llvm.amdgcn.sw.lds.base.table = internal addrspace(4) constant [1 x i32] [i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.sw.lds.k0 to i32)]
+ at llvm.amdgcn.sw.lds.offset.table = internal addrspace(4) constant [1 x [2 x i32]] [[2 x i32] [i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0) to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0) to i32)]]
+
+define void @use_variables() sanitize_address {
+; CHECK-LABEL: define void @use_variables(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr addrspace(4) [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 2147450880
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP3]], 7
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
+; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i8
+; CHECK-NEXT: [[TMP12:%.*]] = icmp sge i8 [[TMP11]], [[TMP7]]
+; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP8]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP13]])
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP16:%.*]], label [[TMP17:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP3]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(4) [[TMP21]] to i64
+; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP23]], 2147450880
+; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr
+; CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[TMP25]], align 1
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i8 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = and i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
+; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i8
+; CHECK-NEXT: [[TMP31:%.*]] = icmp sge i8 [[TMP30]], [[TMP26]]
+; CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP27]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP32]])
+; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i64 [[TMP33]], 0
+; CHECK-NEXT: br i1 [[TMP34]], label [[ASAN_REPORT1:%.*]], label [[TMP37:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP35:%.*]], label [[TMP36:%.*]]
+; CHECK: 35:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP22]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(4) [[TMP21]], align 4
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
+; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
+; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
+; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
+; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
+; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
+; CHECK-NEXT: [[TMP47:%.*]] = add i64 [[TMP46]], 3
+; CHECK-NEXT: [[TMP48:%.*]] = trunc i64 [[TMP47]] to i8
+; CHECK-NEXT: [[TMP49:%.*]] = icmp sge i8 [[TMP48]], [[TMP44]]
+; CHECK-NEXT: [[TMP50:%.*]] = and i1 [[TMP45]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP50]])
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[TMP51]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[ASAN_REPORT2:%.*]], label [[TMP55:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP53:%.*]], label [[TMP54:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP40]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP54]]
+; CHECK: 54:
+; CHECK-NEXT: br label [[TMP55]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(3) [[TMP39]], align 4
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP20]], i32 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(4) [[TMP59]] to i64
+; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP60]], 3
+; CHECK-NEXT: [[TMP62:%.*]] = add i64 [[TMP61]], 2147450880
+; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr
+; CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[TMP63]], align 1
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i8 [[TMP64]], 0
+; CHECK-NEXT: [[TMP66:%.*]] = and i64 [[TMP60]], 7
+; CHECK-NEXT: [[TMP67:%.*]] = add i64 [[TMP66]], 3
+; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i8
+; CHECK-NEXT: [[TMP69:%.*]] = icmp sge i8 [[TMP68]], [[TMP64]]
+; CHECK-NEXT: [[TMP70:%.*]] = and i1 [[TMP65]], [[TMP69]]
+; CHECK-NEXT: [[TMP71:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP70]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i64 [[TMP71]], 0
+; CHECK-NEXT: br i1 [[TMP72]], label [[ASAN_REPORT3:%.*]], label [[TMP75:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP70]], label [[TMP73:%.*]], label [[TMP74:%.*]]
+; CHECK: 73:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP60]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: br label [[TMP75]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(4) [[TMP59]], align 4
+; CHECK-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP78:%.*]] = ptrtoint ptr addrspace(3) [[TMP77]] to i64
+; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP78]], 3
+; CHECK-NEXT: [[TMP80:%.*]] = add i64 [[TMP79]], 2147450880
+; CHECK-NEXT: [[TMP81:%.*]] = inttoptr i64 [[TMP80]] to ptr
+; CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[TMP81]], align 1
+; CHECK-NEXT: [[TMP83:%.*]] = icmp ne i8 [[TMP82]], 0
+; CHECK-NEXT: [[TMP84:%.*]] = and i64 [[TMP78]], 7
+; CHECK-NEXT: [[TMP85:%.*]] = add i64 [[TMP84]], 3
+; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
+; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP82]]
+; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP83]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
+; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
+; CHECK-NEXT: br i1 [[TMP90]], label [[ASAN_REPORT4:%.*]], label [[TMP93:%.*]], !prof [[PROF0]]
+; CHECK: asan.report4:
+; CHECK-NEXT: br i1 [[TMP88]], label [[TMP91:%.*]], label [[TMP92:%.*]]
+; CHECK: 91:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP78]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP92]]
+; CHECK: 92:
+; CHECK-NEXT: br label [[TMP93]]
+; CHECK: 93:
+; CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(3) [[TMP77]], align 4
+; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP58]], i32 [[TMP94]]
+; CHECK-NEXT: [[TMP96:%.*]] = ptrtoint ptr addrspace(3) [[TMP57]] to i64
+; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP96]], 3
+; CHECK-NEXT: [[TMP98:%.*]] = add i64 [[TMP97]], 2147450880
+; CHECK-NEXT: [[TMP99:%.*]] = inttoptr i64 [[TMP98]] to ptr
+; CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[TMP99]], align 1
+; CHECK-NEXT: [[TMP101:%.*]] = icmp ne i8 [[TMP100]], 0
+; CHECK-NEXT: [[TMP102:%.*]] = and i64 [[TMP96]], 7
+; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i8
+; CHECK-NEXT: [[TMP104:%.*]] = icmp sge i8 [[TMP103]], [[TMP100]]
+; CHECK-NEXT: [[TMP105:%.*]] = and i1 [[TMP101]], [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP105]])
+; CHECK-NEXT: [[TMP107:%.*]] = icmp ne i64 [[TMP106]], 0
+; CHECK-NEXT: br i1 [[TMP107]], label [[ASAN_REPORT5:%.*]], label [[TMP110:%.*]], !prof [[PROF0]]
+; CHECK: asan.report5:
+; CHECK-NEXT: br i1 [[TMP105]], label [[TMP108:%.*]], label [[TMP109:%.*]]
+; CHECK: 108:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP96]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP109]]
+; CHECK: 109:
+; CHECK-NEXT: br label [[TMP110]]
+; CHECK: 110:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP57]], align 4
+; CHECK-NEXT: [[TMP111:%.*]] = ptrtoint ptr addrspace(3) [[TMP95]] to i64
+; CHECK-NEXT: [[TMP112:%.*]] = lshr i64 [[TMP111]], 3
+; CHECK-NEXT: [[TMP113:%.*]] = add i64 [[TMP112]], 2147450880
+; CHECK-NEXT: [[TMP114:%.*]] = inttoptr i64 [[TMP113]] to ptr
+; CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[TMP114]], align 1
+; CHECK-NEXT: [[TMP116:%.*]] = icmp ne i8 [[TMP115]], 0
+; CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP111]], 7
+; CHECK-NEXT: [[TMP118:%.*]] = trunc i64 [[TMP117]] to i8
+; CHECK-NEXT: [[TMP119:%.*]] = icmp sge i8 [[TMP118]], [[TMP115]]
+; CHECK-NEXT: [[TMP120:%.*]] = and i1 [[TMP116]], [[TMP119]]
+; CHECK-NEXT: [[TMP121:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP120]])
+; CHECK-NEXT: [[TMP122:%.*]] = icmp ne i64 [[TMP121]], 0
+; CHECK-NEXT: br i1 [[TMP122]], label [[ASAN_REPORT6:%.*]], label [[TMP125:%.*]], !prof [[PROF0]]
+; CHECK: asan.report6:
+; CHECK-NEXT: br i1 [[TMP120]], label [[TMP123:%.*]], label [[TMP124:%.*]]
+; CHECK: 123:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP111]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP124]]
+; CHECK: 124:
+; CHECK-NEXT: br label [[TMP125]]
+; CHECK: 125:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP95]], align 8
+; CHECK-NEXT: ret void
+;
+ %1 = call i32 @llvm.amdgcn.lds.kernel.id()
+ %2 = getelementptr inbounds [1 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 %1
+ %3 = load i32, ptr addrspace(4) %2, align 4
+ %4 = inttoptr i32 %3 to ptr addrspace(3)
+ %5 = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 0
+ %6 = load i32, ptr addrspace(4) %5, align 4
+ %7 = inttoptr i32 %6 to ptr addrspace(3)
+ %8 = load i32, ptr addrspace(3) %7, align 4
+ %9 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %4, i32 %8
+ %10 = inttoptr i32 %3 to ptr addrspace(3)
+ %11 = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 1
+ %12 = load i32, ptr addrspace(4) %11, align 4
+ %13 = inttoptr i32 %12 to ptr addrspace(3)
+ %14 = load i32, ptr addrspace(3) %13, align 4
+ %15 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %10, i32 %14
+ store i8 3, ptr addrspace(3) %9, align 4
+ store i8 3, ptr addrspace(3) %15, align 8
+ ret void
+}
+
+define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0]] !llvm.amdgcn.lds.kernel.id [[META1:![0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP33:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i32 15
+; CHECK-NEXT: store i64 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr addrspace(4) [[TMP10]] to i64
+; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 3
+; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 2147450880
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
+; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP15]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP16]])
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[TMP17]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[ASAN_REPORT:%.*]], label [[TMP21:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP19:%.*]], label [[TMP20:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP11]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP20]]
+; CHECK: 20:
+; CHECK-NEXT: br label [[TMP21]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP24:%.*]] = udiv i64 [[TMP23]], 8
+; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP24]], 8
+; CHECK-NEXT: store i64 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP8]], [[TMP25]]
+; CHECK-NEXT: store i64 [[TMP26]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+; CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = udiv i64 [[TMP28]], 8
+; CHECK-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], 8
+; CHECK-NEXT: store i64 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP33]]
+; CHECK: 33:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP34]]
+; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP36]]
+; CHECK-NEXT: call void @use_variables()
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(3) [[TMP35]] to i64
+; CHECK-NEXT: [[TMP39:%.*]] = lshr i64 [[TMP38]], 3
+; CHECK-NEXT: [[TMP40:%.*]] = add i64 [[TMP39]], 2147450880
+; CHECK-NEXT: [[TMP41:%.*]] = inttoptr i64 [[TMP40]] to ptr
+; CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[TMP41]], align 1
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i8 [[TMP42]], 0
+; CHECK-NEXT: [[TMP44:%.*]] = and i64 [[TMP38]], 7
+; CHECK-NEXT: [[TMP45:%.*]] = trunc i64 [[TMP44]] to i8
+; CHECK-NEXT: [[TMP46:%.*]] = icmp sge i8 [[TMP45]], [[TMP42]]
+; CHECK-NEXT: [[TMP47:%.*]] = and i1 [[TMP43]], [[TMP46]]
+; CHECK-NEXT: [[TMP48:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP47]])
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[TMP48]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[ASAN_REPORT1:%.*]], label [[TMP52:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP50:%.*]], label [[TMP51:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP38]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 1
+; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
+; CHECK-NEXT: [[TMP54:%.*]] = add i64 [[TMP53]], 3
+; CHECK-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP56:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
+; CHECK-NEXT: [[TMP57:%.*]] = lshr i64 [[TMP56]], 3
+; CHECK-NEXT: [[TMP58:%.*]] = add i64 [[TMP57]], 2147450880
+; CHECK-NEXT: [[TMP59:%.*]] = inttoptr i64 [[TMP58]] to ptr
+; CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[TMP59]], align 1
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i8 [[TMP60]], 0
+; CHECK-NEXT: [[TMP62:%.*]] = and i64 [[TMP56]], 7
+; CHECK-NEXT: [[TMP63:%.*]] = trunc i64 [[TMP62]] to i8
+; CHECK-NEXT: [[TMP64:%.*]] = icmp sge i8 [[TMP63]], [[TMP60]]
+; CHECK-NEXT: [[TMP65:%.*]] = and i1 [[TMP61]], [[TMP64]]
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP65]])
+; CHECK-NEXT: [[TMP67:%.*]] = icmp ne i64 [[TMP66]], 0
+; CHECK-NEXT: br i1 [[TMP67]], label [[ASAN_REPORT2:%.*]], label [[TMP70:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP68:%.*]], label [[TMP69:%.*]]
+; CHECK: 68:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP56]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP69]]
+; CHECK: 69:
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr addrspace(3) [[TMP55]] to i64
+; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP71]], 3
+; CHECK-NEXT: [[TMP73:%.*]] = add i64 [[TMP72]], 2147450880
+; CHECK-NEXT: [[TMP74:%.*]] = inttoptr i64 [[TMP73]] to ptr
+; CHECK-NEXT: [[TMP75:%.*]] = load i8, ptr [[TMP74]], align 1
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i8 [[TMP75]], 0
+; CHECK-NEXT: [[TMP77:%.*]] = and i64 [[TMP71]], 7
+; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i8
+; CHECK-NEXT: [[TMP79:%.*]] = icmp sge i8 [[TMP78]], [[TMP75]]
+; CHECK-NEXT: [[TMP80:%.*]] = and i1 [[TMP76]], [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP80]])
+; CHECK-NEXT: [[TMP82:%.*]] = icmp ne i64 [[TMP81]], 0
+; CHECK-NEXT: br i1 [[TMP82]], label [[ASAN_REPORT3:%.*]], label [[TMP85:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP83:%.*]], label [[TMP84:%.*]]
+; CHECK: 83:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP71]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP37]], align 2
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP86:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP86]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %22
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %10 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %9, i32 15
+ store i64 %8, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+ %11 = load i64, ptr addrspace(4) %10, align 8
+ %12 = add i64 %11, 7
+ %13 = udiv i64 %12, 8
+ %14 = mul i64 %13, 8
+ store i64 %14, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+ %15 = add i64 %8, %14
+ store i64 %15, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+ %16 = load i64, ptr addrspace(4) %10, align 8
+ %17 = add i64 %16, 7
+ %18 = udiv i64 %17, 8
+ %19 = mul i64 %18, 8
+ store i64 %19, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+ %20 = add i64 %15, %19
+ %21 = call ptr addrspace(1) @malloc(i64 %20)
+ store ptr addrspace(1) %21, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %22
+
+22: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %23 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %24 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %23
+ %25 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+ %26 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %25
+ call void @use_variables()
+ store i8 7, ptr addrspace(3) %24, align 1
+ store i32 8, ptr addrspace(3) %26, align 2
+ br label %CondFree
+
+CondFree: ; preds = %22
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %27 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %27)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.lds.kernel.id() #0
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+
+!0 = !{i32 0}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+; CHECK: [[META1]] = !{i32 0}
+;.
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-lds-test.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-lds-test.ll
new file mode 100755
index 000000000000000..42f7e253ee59ff6
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-lds-test.ll
@@ -0,0 +1,199 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 1
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type zeroinitializer, no_sanitize_address
+
+define amdgpu_kernel void @k0() sanitize_address {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP30:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i32 15
+; CHECK-NEXT: store i64 0, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 8
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr addrspace(4) [[TMP7]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 2147450880
+; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
+; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP13]])
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP16:%.*]], label [[TMP17:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP8]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr addrspace(4) [[TMP7]], align 8
+; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP19]], 0
+; CHECK-NEXT: [[TMP21:%.*]] = udiv i64 [[TMP20]], 1
+; CHECK-NEXT: [[TMP22:%.*]] = mul i64 [[TMP21]], 1
+; CHECK-NEXT: store i64 [[TMP22]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 0, [[TMP22]]
+; CHECK-NEXT: store i64 [[TMP23]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr addrspace(4) [[TMP7]], align 8
+; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[TMP24]], 0
+; CHECK-NEXT: [[TMP26:%.*]] = udiv i64 [[TMP25]], 1
+; CHECK-NEXT: [[TMP27:%.*]] = mul i64 [[TMP26]], 1
+; CHECK-NEXT: store i64 [[TMP27]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP23]], [[TMP27]]
+; CHECK-NEXT: [[TMP29:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP28]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP29]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP30]]
+; CHECK: 30:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP18]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP33]]
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i64
+; CHECK-NEXT: [[TMP36:%.*]] = lshr i64 [[TMP35]], 3
+; CHECK-NEXT: [[TMP37:%.*]] = add i64 [[TMP36]], 2147450880
+; CHECK-NEXT: [[TMP38:%.*]] = inttoptr i64 [[TMP37]] to ptr
+; CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[TMP38]], align 1
+; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i8 [[TMP39]], 0
+; CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP35]], 7
+; CHECK-NEXT: [[TMP42:%.*]] = trunc i64 [[TMP41]] to i8
+; CHECK-NEXT: [[TMP43:%.*]] = icmp sge i8 [[TMP42]], [[TMP39]]
+; CHECK-NEXT: [[TMP44:%.*]] = and i1 [[TMP40]], [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP44]])
+; CHECK-NEXT: [[TMP46:%.*]] = icmp ne i64 [[TMP45]], 0
+; CHECK-NEXT: br i1 [[TMP46]], label [[ASAN_REPORT1:%.*]], label [[TMP49:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP44]], label [[TMP47:%.*]], label [[TMP48:%.*]]
+; CHECK: 47:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP35]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP48]]
+; CHECK: 48:
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP32]], align 4
+; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr addrspace(3) [[TMP34]] to i64
+; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP50]], 3
+; CHECK-NEXT: [[TMP52:%.*]] = add i64 [[TMP51]], 2147450880
+; CHECK-NEXT: [[TMP53:%.*]] = inttoptr i64 [[TMP52]] to ptr
+; CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[TMP53]], align 1
+; CHECK-NEXT: [[TMP55:%.*]] = icmp ne i8 [[TMP54]], 0
+; CHECK-NEXT: [[TMP56:%.*]] = and i64 [[TMP50]], 7
+; CHECK-NEXT: [[TMP57:%.*]] = trunc i64 [[TMP56]] to i8
+; CHECK-NEXT: [[TMP58:%.*]] = icmp sge i8 [[TMP57]], [[TMP54]]
+; CHECK-NEXT: [[TMP59:%.*]] = and i1 [[TMP55]], [[TMP58]]
+; CHECK-NEXT: [[TMP60:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP59]])
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[TMP60]], 0
+; CHECK-NEXT: br i1 [[TMP61]], label [[ASAN_REPORT2:%.*]], label [[TMP64:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP59]], label [[TMP62:%.*]], label [[TMP63:%.*]]
+; CHECK: 62:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP50]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP63]]
+; CHECK: 63:
+; CHECK-NEXT: br label [[TMP64]]
+; CHECK: 64:
+; CHECK-NEXT: store i8 8, ptr addrspace(3) [[TMP34]], align 8
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP65:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP65]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %19
+
+Malloc: ; preds = %WId
+ %6 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %7 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %6, i32 15
+ store i64 0, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 8
+ %8 = load i64, ptr addrspace(4) %7, align 8
+ %9 = add i64 %8, 0
+ %10 = udiv i64 %9, 1
+ %11 = mul i64 %10, 1
+ store i64 %11, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 1), align 8
+ %12 = add i64 0, %11
+ store i64 %12, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+ %13 = load i64, ptr addrspace(4) %7, align 8
+ %14 = add i64 %13, 0
+ %15 = udiv i64 %14, 1
+ %16 = mul i64 %15, 1
+ store i64 %16, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+ %17 = add i64 %12, %16
+ %18 = call ptr addrspace(1) @malloc(i64 %17)
+ store ptr addrspace(1) %18, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %19
+
+19: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %20 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %21 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %20
+ %22 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+ %23 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %22
+ store i8 7, ptr addrspace(3) %21, align 4
+ store i8 8, ptr addrspace(3) %23, align 8
+ br label %CondFree
+
+CondFree: ; preds = %19
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %24 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %24)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+;.
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll
new file mode 100755
index 000000000000000..dac53c55725aafa
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll
@@ -0,0 +1,787 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+%llvm.amdgcn.sw.lds.k1.md.type = type { %llvm.amdgcn.sw.lds.k1.md.item, %llvm.amdgcn.sw.lds.k1.md.item, %llvm.amdgcn.sw.lds.k1.md.item, %llvm.amdgcn.sw.lds.k1.md.item, %llvm.amdgcn.sw.lds.k1.md.item }
+%llvm.amdgcn.sw.lds.k1.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 0 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 0 } }, no_sanitize_address
+ at llvm.amdgcn.sw.lds.k1 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k1.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k1.md.type { %llvm.amdgcn.sw.lds.k1.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 16, i32 0 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 16, i32 0 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 16, i32 0 } }, no_sanitize_address
+ at llvm.amdgcn.sw.lds.base.table = internal addrspace(4) constant [2 x i32] [i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.sw.lds.k0 to i32), i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.sw.lds.k1 to i32)]
+ at llvm.amdgcn.sw.lds.offset.table = internal addrspace(4) constant [2 x [4 x i32]] [[4 x i32] [i32 ptrtoint (ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md to i32), i32 poison, i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0) to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0) to i32)], [4 x i32] [i32 ptrtoint (ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 0) to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0) to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0) to i32)]]
+
+define void @use_variables_1() sanitize_address {
+; CHECK-LABEL: define void @use_variables_1(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr addrspace(4) [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 2147450880
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP3]], 7
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
+; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i8
+; CHECK-NEXT: [[TMP12:%.*]] = icmp sge i8 [[TMP11]], [[TMP7]]
+; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP8]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP13]])
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP16:%.*]], label [[TMP17:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP3]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(4) [[TMP21]] to i64
+; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP23]], 2147450880
+; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr
+; CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[TMP25]], align 1
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i8 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = and i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
+; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i8
+; CHECK-NEXT: [[TMP31:%.*]] = icmp sge i8 [[TMP30]], [[TMP26]]
+; CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP27]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP32]])
+; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i64 [[TMP33]], 0
+; CHECK-NEXT: br i1 [[TMP34]], label [[ASAN_REPORT1:%.*]], label [[TMP37:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP35:%.*]], label [[TMP36:%.*]]
+; CHECK: 35:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP22]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(4) [[TMP21]], align 4
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
+; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
+; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
+; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
+; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
+; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
+; CHECK-NEXT: [[TMP47:%.*]] = add i64 [[TMP46]], 3
+; CHECK-NEXT: [[TMP48:%.*]] = trunc i64 [[TMP47]] to i8
+; CHECK-NEXT: [[TMP49:%.*]] = icmp sge i8 [[TMP48]], [[TMP44]]
+; CHECK-NEXT: [[TMP50:%.*]] = and i1 [[TMP45]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP50]])
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[TMP51]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[ASAN_REPORT2:%.*]], label [[TMP55:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP53:%.*]], label [[TMP54:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP40]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP54]]
+; CHECK: 54:
+; CHECK-NEXT: br label [[TMP55]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(3) [[TMP39]], align 4
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP20]], i32 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(4) [[TMP59]] to i64
+; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP60]], 3
+; CHECK-NEXT: [[TMP62:%.*]] = add i64 [[TMP61]], 2147450880
+; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr
+; CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[TMP63]], align 1
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i8 [[TMP64]], 0
+; CHECK-NEXT: [[TMP66:%.*]] = and i64 [[TMP60]], 7
+; CHECK-NEXT: [[TMP67:%.*]] = add i64 [[TMP66]], 3
+; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i8
+; CHECK-NEXT: [[TMP69:%.*]] = icmp sge i8 [[TMP68]], [[TMP64]]
+; CHECK-NEXT: [[TMP70:%.*]] = and i1 [[TMP65]], [[TMP69]]
+; CHECK-NEXT: [[TMP71:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP70]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i64 [[TMP71]], 0
+; CHECK-NEXT: br i1 [[TMP72]], label [[ASAN_REPORT3:%.*]], label [[TMP75:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP70]], label [[TMP73:%.*]], label [[TMP74:%.*]]
+; CHECK: 73:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP60]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: br label [[TMP75]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(4) [[TMP59]], align 4
+; CHECK-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP78:%.*]] = ptrtoint ptr addrspace(3) [[TMP77]] to i64
+; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP78]], 3
+; CHECK-NEXT: [[TMP80:%.*]] = add i64 [[TMP79]], 2147450880
+; CHECK-NEXT: [[TMP81:%.*]] = inttoptr i64 [[TMP80]] to ptr
+; CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[TMP81]], align 1
+; CHECK-NEXT: [[TMP83:%.*]] = icmp ne i8 [[TMP82]], 0
+; CHECK-NEXT: [[TMP84:%.*]] = and i64 [[TMP78]], 7
+; CHECK-NEXT: [[TMP85:%.*]] = add i64 [[TMP84]], 3
+; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
+; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP82]]
+; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP83]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
+; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
+; CHECK-NEXT: br i1 [[TMP90]], label [[ASAN_REPORT4:%.*]], label [[TMP93:%.*]], !prof [[PROF0]]
+; CHECK: asan.report4:
+; CHECK-NEXT: br i1 [[TMP88]], label [[TMP91:%.*]], label [[TMP92:%.*]]
+; CHECK: 91:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP78]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP92]]
+; CHECK: 92:
+; CHECK-NEXT: br label [[TMP93]]
+; CHECK: 93:
+; CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(3) [[TMP77]], align 4
+; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP58]], i32 [[TMP94]]
+; CHECK-NEXT: [[TMP96:%.*]] = ptrtoint ptr addrspace(3) [[TMP57]] to i64
+; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP96]], 3
+; CHECK-NEXT: [[TMP98:%.*]] = add i64 [[TMP97]], 2147450880
+; CHECK-NEXT: [[TMP99:%.*]] = inttoptr i64 [[TMP98]] to ptr
+; CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[TMP99]], align 1
+; CHECK-NEXT: [[TMP101:%.*]] = icmp ne i8 [[TMP100]], 0
+; CHECK-NEXT: [[TMP102:%.*]] = and i64 [[TMP96]], 7
+; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i8
+; CHECK-NEXT: [[TMP104:%.*]] = icmp sge i8 [[TMP103]], [[TMP100]]
+; CHECK-NEXT: [[TMP105:%.*]] = and i1 [[TMP101]], [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP105]])
+; CHECK-NEXT: [[TMP107:%.*]] = icmp ne i64 [[TMP106]], 0
+; CHECK-NEXT: br i1 [[TMP107]], label [[ASAN_REPORT5:%.*]], label [[TMP110:%.*]], !prof [[PROF0]]
+; CHECK: asan.report5:
+; CHECK-NEXT: br i1 [[TMP105]], label [[TMP108:%.*]], label [[TMP109:%.*]]
+; CHECK: 108:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP96]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP109]]
+; CHECK: 109:
+; CHECK-NEXT: br label [[TMP110]]
+; CHECK: 110:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP57]], align 4
+; CHECK-NEXT: [[TMP111:%.*]] = ptrtoint ptr addrspace(3) [[TMP95]] to i64
+; CHECK-NEXT: [[TMP112:%.*]] = lshr i64 [[TMP111]], 3
+; CHECK-NEXT: [[TMP113:%.*]] = add i64 [[TMP112]], 2147450880
+; CHECK-NEXT: [[TMP114:%.*]] = inttoptr i64 [[TMP113]] to ptr
+; CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[TMP114]], align 1
+; CHECK-NEXT: [[TMP116:%.*]] = icmp ne i8 [[TMP115]], 0
+; CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP111]], 7
+; CHECK-NEXT: [[TMP118:%.*]] = trunc i64 [[TMP117]] to i8
+; CHECK-NEXT: [[TMP119:%.*]] = icmp sge i8 [[TMP118]], [[TMP115]]
+; CHECK-NEXT: [[TMP120:%.*]] = and i1 [[TMP116]], [[TMP119]]
+; CHECK-NEXT: [[TMP121:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP120]])
+; CHECK-NEXT: [[TMP122:%.*]] = icmp ne i64 [[TMP121]], 0
+; CHECK-NEXT: br i1 [[TMP122]], label [[ASAN_REPORT6:%.*]], label [[TMP125:%.*]], !prof [[PROF0]]
+; CHECK: asan.report6:
+; CHECK-NEXT: br i1 [[TMP120]], label [[TMP123:%.*]], label [[TMP124:%.*]]
+; CHECK: 123:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP111]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP124]]
+; CHECK: 124:
+; CHECK-NEXT: br label [[TMP125]]
+; CHECK: 125:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP95]], align 8
+; CHECK-NEXT: ret void
+;
+ %1 = call i32 @llvm.amdgcn.lds.kernel.id()
+ %2 = getelementptr inbounds [2 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 %1
+ %3 = load i32, ptr addrspace(4) %2, align 4
+ %4 = inttoptr i32 %3 to ptr addrspace(3)
+ %5 = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 2
+ %6 = load i32, ptr addrspace(4) %5, align 4
+ %7 = inttoptr i32 %6 to ptr addrspace(3)
+ %8 = load i32, ptr addrspace(3) %7, align 4
+ %9 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %4, i32 %8
+ %10 = inttoptr i32 %3 to ptr addrspace(3)
+ %11 = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 3
+ %12 = load i32, ptr addrspace(4) %11, align 4
+ %13 = inttoptr i32 %12 to ptr addrspace(3)
+ %14 = load i32, ptr addrspace(3) %13, align 4
+ %15 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %10, i32 %14
+ store i8 3, ptr addrspace(3) %9, align 4
+ store i8 3, ptr addrspace(3) %15, align 8
+ ret void
+}
+
+define void @use_variables_2() sanitize_address {
+; CHECK-LABEL: define void @use_variables_2(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr addrspace(4) [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 2147450880
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP3]], 7
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
+; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i8
+; CHECK-NEXT: [[TMP12:%.*]] = icmp sge i8 [[TMP11]], [[TMP7]]
+; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP8]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP13]])
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP18:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP16:%.*]], label [[TMP17:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP3]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(4) [[TMP21]] to i64
+; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP23]], 2147450880
+; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr
+; CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[TMP25]], align 1
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i8 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = and i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
+; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i8
+; CHECK-NEXT: [[TMP31:%.*]] = icmp sge i8 [[TMP30]], [[TMP26]]
+; CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP27]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP32]])
+; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i64 [[TMP33]], 0
+; CHECK-NEXT: br i1 [[TMP34]], label [[ASAN_REPORT1:%.*]], label [[TMP37:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP35:%.*]], label [[TMP36:%.*]]
+; CHECK: 35:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP22]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(4) [[TMP21]], align 4
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
+; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
+; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
+; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
+; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
+; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
+; CHECK-NEXT: [[TMP47:%.*]] = add i64 [[TMP46]], 3
+; CHECK-NEXT: [[TMP48:%.*]] = trunc i64 [[TMP47]] to i8
+; CHECK-NEXT: [[TMP49:%.*]] = icmp sge i8 [[TMP48]], [[TMP44]]
+; CHECK-NEXT: [[TMP50:%.*]] = and i1 [[TMP45]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP50]])
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[TMP51]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[ASAN_REPORT2:%.*]], label [[TMP55:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP53:%.*]], label [[TMP54:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP40]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP54]]
+; CHECK: 54:
+; CHECK-NEXT: br label [[TMP55]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(3) [[TMP39]], align 4
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP20]], i32 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(4) [[TMP59]] to i64
+; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP60]], 3
+; CHECK-NEXT: [[TMP62:%.*]] = add i64 [[TMP61]], 2147450880
+; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr
+; CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[TMP63]], align 1
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i8 [[TMP64]], 0
+; CHECK-NEXT: [[TMP66:%.*]] = and i64 [[TMP60]], 7
+; CHECK-NEXT: [[TMP67:%.*]] = add i64 [[TMP66]], 3
+; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i8
+; CHECK-NEXT: [[TMP69:%.*]] = icmp sge i8 [[TMP68]], [[TMP64]]
+; CHECK-NEXT: [[TMP70:%.*]] = and i1 [[TMP65]], [[TMP69]]
+; CHECK-NEXT: [[TMP71:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP70]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i64 [[TMP71]], 0
+; CHECK-NEXT: br i1 [[TMP72]], label [[ASAN_REPORT3:%.*]], label [[TMP75:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP70]], label [[TMP73:%.*]], label [[TMP74:%.*]]
+; CHECK: 73:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP60]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: br label [[TMP75]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(4) [[TMP59]], align 4
+; CHECK-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP78:%.*]] = ptrtoint ptr addrspace(3) [[TMP77]] to i64
+; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP78]], 3
+; CHECK-NEXT: [[TMP80:%.*]] = add i64 [[TMP79]], 2147450880
+; CHECK-NEXT: [[TMP81:%.*]] = inttoptr i64 [[TMP80]] to ptr
+; CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[TMP81]], align 1
+; CHECK-NEXT: [[TMP83:%.*]] = icmp ne i8 [[TMP82]], 0
+; CHECK-NEXT: [[TMP84:%.*]] = and i64 [[TMP78]], 7
+; CHECK-NEXT: [[TMP85:%.*]] = add i64 [[TMP84]], 3
+; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
+; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP82]]
+; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP83]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
+; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
+; CHECK-NEXT: br i1 [[TMP90]], label [[ASAN_REPORT4:%.*]], label [[TMP93:%.*]], !prof [[PROF0]]
+; CHECK: asan.report4:
+; CHECK-NEXT: br i1 [[TMP88]], label [[TMP91:%.*]], label [[TMP92:%.*]]
+; CHECK: 91:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP78]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP92]]
+; CHECK: 92:
+; CHECK-NEXT: br label [[TMP93]]
+; CHECK: 93:
+; CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(3) [[TMP77]], align 4
+; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP58]], i32 [[TMP94]]
+; CHECK-NEXT: [[TMP96:%.*]] = ptrtoint ptr addrspace(3) [[TMP57]] to i64
+; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP96]], 3
+; CHECK-NEXT: [[TMP98:%.*]] = add i64 [[TMP97]], 2147450880
+; CHECK-NEXT: [[TMP99:%.*]] = inttoptr i64 [[TMP98]] to ptr
+; CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[TMP99]], align 1
+; CHECK-NEXT: [[TMP101:%.*]] = icmp ne i8 [[TMP100]], 0
+; CHECK-NEXT: [[TMP102:%.*]] = and i64 [[TMP96]], 7
+; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i8
+; CHECK-NEXT: [[TMP104:%.*]] = icmp sge i8 [[TMP103]], [[TMP100]]
+; CHECK-NEXT: [[TMP105:%.*]] = and i1 [[TMP101]], [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP105]])
+; CHECK-NEXT: [[TMP107:%.*]] = icmp ne i64 [[TMP106]], 0
+; CHECK-NEXT: br i1 [[TMP107]], label [[ASAN_REPORT5:%.*]], label [[TMP110:%.*]], !prof [[PROF0]]
+; CHECK: asan.report5:
+; CHECK-NEXT: br i1 [[TMP105]], label [[TMP108:%.*]], label [[TMP109:%.*]]
+; CHECK: 108:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP96]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP109]]
+; CHECK: 109:
+; CHECK-NEXT: br label [[TMP110]]
+; CHECK: 110:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP57]], align 1
+; CHECK-NEXT: [[TMP111:%.*]] = ptrtoint ptr addrspace(3) [[TMP95]] to i64
+; CHECK-NEXT: [[TMP112:%.*]] = add i64 [[TMP111]], 3
+; CHECK-NEXT: [[TMP113:%.*]] = inttoptr i64 [[TMP112]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP114:%.*]] = ptrtoint ptr addrspace(3) [[TMP95]] to i64
+; CHECK-NEXT: [[TMP115:%.*]] = lshr i64 [[TMP114]], 3
+; CHECK-NEXT: [[TMP116:%.*]] = add i64 [[TMP115]], 2147450880
+; CHECK-NEXT: [[TMP117:%.*]] = inttoptr i64 [[TMP116]] to ptr
+; CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[TMP117]], align 1
+; CHECK-NEXT: [[TMP119:%.*]] = icmp ne i8 [[TMP118]], 0
+; CHECK-NEXT: [[TMP120:%.*]] = and i64 [[TMP114]], 7
+; CHECK-NEXT: [[TMP121:%.*]] = trunc i64 [[TMP120]] to i8
+; CHECK-NEXT: [[TMP122:%.*]] = icmp sge i8 [[TMP121]], [[TMP118]]
+; CHECK-NEXT: [[TMP123:%.*]] = and i1 [[TMP119]], [[TMP122]]
+; CHECK-NEXT: [[TMP124:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP123]])
+; CHECK-NEXT: [[TMP125:%.*]] = icmp ne i64 [[TMP124]], 0
+; CHECK-NEXT: br i1 [[TMP125]], label [[ASAN_REPORT6:%.*]], label [[TMP128:%.*]], !prof [[PROF0]]
+; CHECK: asan.report6:
+; CHECK-NEXT: br i1 [[TMP123]], label [[TMP126:%.*]], label [[TMP127:%.*]]
+; CHECK: 126:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP114]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP127]]
+; CHECK: 127:
+; CHECK-NEXT: br label [[TMP128]]
+; CHECK: 128:
+; CHECK-NEXT: [[TMP129:%.*]] = ptrtoint ptr addrspace(3) [[TMP113]] to i64
+; CHECK-NEXT: [[TMP130:%.*]] = lshr i64 [[TMP129]], 3
+; CHECK-NEXT: [[TMP131:%.*]] = add i64 [[TMP130]], 2147450880
+; CHECK-NEXT: [[TMP132:%.*]] = inttoptr i64 [[TMP131]] to ptr
+; CHECK-NEXT: [[TMP133:%.*]] = load i8, ptr [[TMP132]], align 1
+; CHECK-NEXT: [[TMP134:%.*]] = icmp ne i8 [[TMP133]], 0
+; CHECK-NEXT: [[TMP135:%.*]] = and i64 [[TMP129]], 7
+; CHECK-NEXT: [[TMP136:%.*]] = trunc i64 [[TMP135]] to i8
+; CHECK-NEXT: [[TMP137:%.*]] = icmp sge i8 [[TMP136]], [[TMP133]]
+; CHECK-NEXT: [[TMP138:%.*]] = and i1 [[TMP134]], [[TMP137]]
+; CHECK-NEXT: [[TMP139:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP138]])
+; CHECK-NEXT: [[TMP140:%.*]] = icmp ne i64 [[TMP139]], 0
+; CHECK-NEXT: br i1 [[TMP140]], label [[ASAN_REPORT7:%.*]], label [[TMP143:%.*]], !prof [[PROF0]]
+; CHECK: asan.report7:
+; CHECK-NEXT: br i1 [[TMP138]], label [[TMP141:%.*]], label [[TMP142:%.*]]
+; CHECK: 141:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP129]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP142]]
+; CHECK: 142:
+; CHECK-NEXT: br label [[TMP143]]
+; CHECK: 143:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP95]], align 2
+; CHECK-NEXT: ret void
+;
+ %1 = call i32 @llvm.amdgcn.lds.kernel.id()
+ %2 = getelementptr inbounds [2 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 %1
+ %3 = load i32, ptr addrspace(4) %2, align 4
+ %4 = inttoptr i32 %3 to ptr addrspace(3)
+ %5 = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 0
+ %6 = load i32, ptr addrspace(4) %5, align 4
+ %7 = inttoptr i32 %6 to ptr addrspace(3)
+ %8 = load i32, ptr addrspace(3) %7, align 4
+ %9 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %4, i32 %8
+ %10 = inttoptr i32 %3 to ptr addrspace(3)
+ %11 = getelementptr inbounds [2 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 1
+ %12 = load i32, ptr addrspace(4) %11, align 4
+ %13 = inttoptr i32 %12 to ptr addrspace(3)
+ %14 = load i32, ptr addrspace(3) %13, align 4
+ %15 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %10, i32 %14
+ store i8 7, ptr addrspace(3) %9, align 1
+ store i32 8, ptr addrspace(3) %15, align 2
+ ret void
+}
+
+define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0]] !llvm.amdgcn.lds.kernel.id [[META1:![0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP33:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i32 15
+; CHECK-NEXT: store i64 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr addrspace(4) [[TMP10]] to i64
+; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 3
+; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 2147450880
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
+; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP15]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP16]])
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[TMP17]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[ASAN_REPORT:%.*]], label [[TMP21:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP19:%.*]], label [[TMP20:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP11]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP20]]
+; CHECK: 20:
+; CHECK-NEXT: br label [[TMP21]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP24:%.*]] = udiv i64 [[TMP23]], 8
+; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP24]], 8
+; CHECK-NEXT: store i64 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP8]], [[TMP25]]
+; CHECK-NEXT: store i64 [[TMP26]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+; CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = udiv i64 [[TMP28]], 8
+; CHECK-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], 8
+; CHECK-NEXT: store i64 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP33]]
+; CHECK: 33:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP34]]
+; CHECK-NEXT: call void @use_variables_1()
+; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr addrspace(3) [[TMP35]] to i64
+; CHECK-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 3
+; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP37]], 2147450880
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to ptr
+; CHECK-NEXT: [[TMP40:%.*]] = load i8, ptr [[TMP39]], align 1
+; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i8 [[TMP40]], 0
+; CHECK-NEXT: [[TMP42:%.*]] = and i64 [[TMP36]], 7
+; CHECK-NEXT: [[TMP43:%.*]] = trunc i64 [[TMP42]] to i8
+; CHECK-NEXT: [[TMP44:%.*]] = icmp sge i8 [[TMP43]], [[TMP40]]
+; CHECK-NEXT: [[TMP45:%.*]] = and i1 [[TMP41]], [[TMP44]]
+; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP45]])
+; CHECK-NEXT: [[TMP47:%.*]] = icmp ne i64 [[TMP46]], 0
+; CHECK-NEXT: br i1 [[TMP47]], label [[ASAN_REPORT1:%.*]], label [[TMP50:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP45]], label [[TMP48:%.*]], label [[TMP49:%.*]]
+; CHECK: 48:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP36]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP49]]
+; CHECK: 49:
+; CHECK-NEXT: br label [[TMP50]]
+; CHECK: 50:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 1
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP51:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP51]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %22
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %10 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %9, i32 15
+ store i64 %8, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+ %11 = load i64, ptr addrspace(4) %10, align 8
+ %12 = add i64 %11, 7
+ %13 = udiv i64 %12, 8
+ %14 = mul i64 %13, 8
+ store i64 %14, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+ %15 = add i64 %8, %14
+ store i64 %15, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+ %16 = load i64, ptr addrspace(4) %10, align 8
+ %17 = add i64 %16, 7
+ %18 = udiv i64 %17, 8
+ %19 = mul i64 %18, 8
+ store i64 %19, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+ %20 = add i64 %15, %19
+ %21 = call ptr addrspace(1) @malloc(i64 %20)
+ store ptr addrspace(1) %21, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %22
+
+22: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %23 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %24 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %23
+ call void @use_variables_1()
+ store i8 7, ptr addrspace(3) %24, align 1
+ br label %CondFree
+
+CondFree: ; preds = %22
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %25 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %25)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+define amdgpu_kernel void @k1() sanitize_address !llvm.amdgcn.lds.kernel.id !1 {
+; CHECK-LABEL: define amdgpu_kernel void @k1(
+; CHECK-SAME: ) #[[ATTR0]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP38:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i32 15
+; CHECK-NEXT: store i64 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 8
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr addrspace(4) [[TMP10]] to i64
+; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 3
+; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 2147450880
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
+; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP15]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP16]])
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[TMP17]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[ASAN_REPORT:%.*]], label [[TMP21:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP19:%.*]], label [[TMP20:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP11]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP20]]
+; CHECK: 20:
+; CHECK-NEXT: br label [[TMP21]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP24:%.*]] = udiv i64 [[TMP23]], 8
+; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP24]], 8
+; CHECK-NEXT: store i64 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 8
+; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP8]], [[TMP25]]
+; CHECK-NEXT: store i64 [[TMP26]], ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 8
+; CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = udiv i64 [[TMP28]], 8
+; CHECK-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], 8
+; CHECK-NEXT: store i64 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 8
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: store i64 [[TMP31]], ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0), align 8
+; CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP32]], 7
+; CHECK-NEXT: [[TMP34:%.*]] = udiv i64 [[TMP33]], 8
+; CHECK-NEXT: [[TMP35:%.*]] = mul i64 [[TMP34]], 8
+; CHECK-NEXT: store i64 [[TMP35]], ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 1), align 8
+; CHECK-NEXT: [[TMP36:%.*]] = add i64 [[TMP31]], [[TMP35]]
+; CHECK-NEXT: [[TMP37:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP36]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP37]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8
+; CHECK-NEXT: br label [[TMP38]]
+; CHECK: 38:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, i32 [[TMP39]]
+; CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, i32 [[TMP41]]
+; CHECK-NEXT: call void @use_variables_1()
+; CHECK-NEXT: call void @use_variables_2()
+; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr addrspace(3) [[TMP40]] to i64
+; CHECK-NEXT: [[TMP44:%.*]] = lshr i64 [[TMP43]], 3
+; CHECK-NEXT: [[TMP45:%.*]] = add i64 [[TMP44]], 2147450880
+; CHECK-NEXT: [[TMP46:%.*]] = inttoptr i64 [[TMP45]] to ptr
+; CHECK-NEXT: [[TMP47:%.*]] = load i8, ptr [[TMP46]], align 1
+; CHECK-NEXT: [[TMP48:%.*]] = icmp ne i8 [[TMP47]], 0
+; CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP43]], 7
+; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[TMP49]] to i8
+; CHECK-NEXT: [[TMP51:%.*]] = icmp sge i8 [[TMP50]], [[TMP47]]
+; CHECK-NEXT: [[TMP52:%.*]] = and i1 [[TMP48]], [[TMP51]]
+; CHECK-NEXT: [[TMP53:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP52]])
+; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i64 [[TMP53]], 0
+; CHECK-NEXT: br i1 [[TMP54]], label [[ASAN_REPORT1:%.*]], label [[TMP57:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP52]], label [[TMP55:%.*]], label [[TMP56:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP43]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP56]]
+; CHECK: 56:
+; CHECK-NEXT: br label [[TMP57]]
+; CHECK: 57:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP40]], align 4
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP58:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP58]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %27
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 0), align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %10 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %9, i32 15
+ store i64 %8, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 8
+ %11 = load i64, ptr addrspace(4) %10, align 8
+ %12 = add i64 %11, 7
+ %13 = udiv i64 %12, 8
+ %14 = mul i64 %13, 8
+ store i64 %14, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 8
+ %15 = add i64 %8, %14
+ store i64 %15, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 8
+ %16 = load i64, ptr addrspace(4) %10, align 8
+ %17 = add i64 %16, 7
+ %18 = udiv i64 %17, 8
+ %19 = mul i64 %18, 8
+ store i64 %19, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 8
+ %20 = add i64 %15, %19
+ store i64 %20, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0), align 8
+ %21 = load i64, ptr addrspace(4) %10, align 8
+ %22 = add i64 %21, 7
+ %23 = udiv i64 %22, 8
+ %24 = mul i64 %23, 8
+ store i64 %24, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 1), align 8
+ %25 = add i64 %20, %24
+ %26 = call ptr addrspace(1) @malloc(i64 %25)
+ store ptr addrspace(1) %26, ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8
+ br label %27
+
+27: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %28 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
+ %29 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, i32 %28
+ %30 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
+ %31 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, i32 %30
+ call void @use_variables_1()
+ call void @use_variables_2()
+ store i8 3, ptr addrspace(3) %29, align 4
+ br label %CondFree
+
+CondFree: ; preds = %27
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %32 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8
+ call void @free(ptr %32)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.lds.kernel.id() #0
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+
+!0 = !{i32 0}
+!1 = !{i32 1}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+; CHECK: [[META1]] = !{i32 0}
+; CHECK: [[META2]] = !{i32 1}
+;.
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll
new file mode 100755
index 000000000000000..31dc4da9a9d6bd8
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll
@@ -0,0 +1,441 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 0 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 0 } }, no_sanitize_address
+ at llvm.amdgcn.sw.lds.base.table = internal addrspace(4) constant [1 x i32] [i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.sw.lds.k0 to i32)]
+ at llvm.amdgcn.sw.lds.offset.table = internal addrspace(4) constant [1 x [2 x i32]] [[2 x i32] [i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0) to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0) to i32)]]
+
+define void @use_variables() sanitize_address {
+; CHECK-LABEL: define void @use_variables(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr addrspace(4) [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 2147450880
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP3]], 7
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
+; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i8
+; CHECK-NEXT: [[TMP12:%.*]] = icmp sge i8 [[TMP11]], [[TMP7]]
+; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP8]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP13]])
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP16:%.*]], label [[TMP17:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP3]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(4) [[TMP21]] to i64
+; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP23]], 2147450880
+; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr
+; CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[TMP25]], align 1
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i8 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = and i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
+; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i8
+; CHECK-NEXT: [[TMP31:%.*]] = icmp sge i8 [[TMP30]], [[TMP26]]
+; CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP27]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP32]])
+; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i64 [[TMP33]], 0
+; CHECK-NEXT: br i1 [[TMP34]], label [[ASAN_REPORT1:%.*]], label [[TMP37:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP35:%.*]], label [[TMP36:%.*]]
+; CHECK: 35:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP22]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(4) [[TMP21]], align 4
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
+; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
+; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
+; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
+; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
+; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
+; CHECK-NEXT: [[TMP47:%.*]] = add i64 [[TMP46]], 3
+; CHECK-NEXT: [[TMP48:%.*]] = trunc i64 [[TMP47]] to i8
+; CHECK-NEXT: [[TMP49:%.*]] = icmp sge i8 [[TMP48]], [[TMP44]]
+; CHECK-NEXT: [[TMP50:%.*]] = and i1 [[TMP45]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP50]])
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[TMP51]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[ASAN_REPORT2:%.*]], label [[TMP55:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP53:%.*]], label [[TMP54:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP40]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP54]]
+; CHECK: 54:
+; CHECK-NEXT: br label [[TMP55]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(3) [[TMP39]], align 4
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP20]], i32 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(4) [[TMP59]] to i64
+; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP60]], 3
+; CHECK-NEXT: [[TMP62:%.*]] = add i64 [[TMP61]], 2147450880
+; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr
+; CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[TMP63]], align 1
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i8 [[TMP64]], 0
+; CHECK-NEXT: [[TMP66:%.*]] = and i64 [[TMP60]], 7
+; CHECK-NEXT: [[TMP67:%.*]] = add i64 [[TMP66]], 3
+; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i8
+; CHECK-NEXT: [[TMP69:%.*]] = icmp sge i8 [[TMP68]], [[TMP64]]
+; CHECK-NEXT: [[TMP70:%.*]] = and i1 [[TMP65]], [[TMP69]]
+; CHECK-NEXT: [[TMP71:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP70]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i64 [[TMP71]], 0
+; CHECK-NEXT: br i1 [[TMP72]], label [[ASAN_REPORT3:%.*]], label [[TMP75:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP70]], label [[TMP73:%.*]], label [[TMP74:%.*]]
+; CHECK: 73:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP60]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: br label [[TMP75]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(4) [[TMP59]], align 4
+; CHECK-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP78:%.*]] = ptrtoint ptr addrspace(3) [[TMP77]] to i64
+; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP78]], 3
+; CHECK-NEXT: [[TMP80:%.*]] = add i64 [[TMP79]], 2147450880
+; CHECK-NEXT: [[TMP81:%.*]] = inttoptr i64 [[TMP80]] to ptr
+; CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[TMP81]], align 1
+; CHECK-NEXT: [[TMP83:%.*]] = icmp ne i8 [[TMP82]], 0
+; CHECK-NEXT: [[TMP84:%.*]] = and i64 [[TMP78]], 7
+; CHECK-NEXT: [[TMP85:%.*]] = add i64 [[TMP84]], 3
+; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
+; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP82]]
+; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP83]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
+; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
+; CHECK-NEXT: br i1 [[TMP90]], label [[ASAN_REPORT4:%.*]], label [[TMP93:%.*]], !prof [[PROF0]]
+; CHECK: asan.report4:
+; CHECK-NEXT: br i1 [[TMP88]], label [[TMP91:%.*]], label [[TMP92:%.*]]
+; CHECK: 91:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP78]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP92]]
+; CHECK: 92:
+; CHECK-NEXT: br label [[TMP93]]
+; CHECK: 93:
+; CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(3) [[TMP77]], align 4
+; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP58]], i32 [[TMP94]]
+; CHECK-NEXT: [[TMP96:%.*]] = ptrtoint ptr addrspace(3) [[TMP57]] to i64
+; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP96]], 3
+; CHECK-NEXT: [[TMP98:%.*]] = add i64 [[TMP97]], 2147450880
+; CHECK-NEXT: [[TMP99:%.*]] = inttoptr i64 [[TMP98]] to ptr
+; CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[TMP99]], align 1
+; CHECK-NEXT: [[TMP101:%.*]] = icmp ne i8 [[TMP100]], 0
+; CHECK-NEXT: [[TMP102:%.*]] = and i64 [[TMP96]], 7
+; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i8
+; CHECK-NEXT: [[TMP104:%.*]] = icmp sge i8 [[TMP103]], [[TMP100]]
+; CHECK-NEXT: [[TMP105:%.*]] = and i1 [[TMP101]], [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP105]])
+; CHECK-NEXT: [[TMP107:%.*]] = icmp ne i64 [[TMP106]], 0
+; CHECK-NEXT: br i1 [[TMP107]], label [[ASAN_REPORT5:%.*]], label [[TMP110:%.*]], !prof [[PROF0]]
+; CHECK: asan.report5:
+; CHECK-NEXT: br i1 [[TMP105]], label [[TMP108:%.*]], label [[TMP109:%.*]]
+; CHECK: 108:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP96]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP109]]
+; CHECK: 109:
+; CHECK-NEXT: br label [[TMP110]]
+; CHECK: 110:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP57]], align 4
+; CHECK-NEXT: [[TMP111:%.*]] = ptrtoint ptr addrspace(3) [[TMP95]] to i64
+; CHECK-NEXT: [[TMP112:%.*]] = lshr i64 [[TMP111]], 3
+; CHECK-NEXT: [[TMP113:%.*]] = add i64 [[TMP112]], 2147450880
+; CHECK-NEXT: [[TMP114:%.*]] = inttoptr i64 [[TMP113]] to ptr
+; CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[TMP114]], align 1
+; CHECK-NEXT: [[TMP116:%.*]] = icmp ne i8 [[TMP115]], 0
+; CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP111]], 7
+; CHECK-NEXT: [[TMP118:%.*]] = trunc i64 [[TMP117]] to i8
+; CHECK-NEXT: [[TMP119:%.*]] = icmp sge i8 [[TMP118]], [[TMP115]]
+; CHECK-NEXT: [[TMP120:%.*]] = and i1 [[TMP116]], [[TMP119]]
+; CHECK-NEXT: [[TMP121:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP120]])
+; CHECK-NEXT: [[TMP122:%.*]] = icmp ne i64 [[TMP121]], 0
+; CHECK-NEXT: br i1 [[TMP122]], label [[ASAN_REPORT6:%.*]], label [[TMP125:%.*]], !prof [[PROF0]]
+; CHECK: asan.report6:
+; CHECK-NEXT: br i1 [[TMP120]], label [[TMP123:%.*]], label [[TMP124:%.*]]
+; CHECK: 123:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP111]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP124]]
+; CHECK: 124:
+; CHECK-NEXT: br label [[TMP125]]
+; CHECK: 125:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP95]], align 8
+; CHECK-NEXT: ret void
+;
+ %1 = call i32 @llvm.amdgcn.lds.kernel.id()
+ %2 = getelementptr inbounds [1 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 %1
+ %3 = load i32, ptr addrspace(4) %2, align 4
+ %4 = inttoptr i32 %3 to ptr addrspace(3)
+ %5 = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 0
+ %6 = load i32, ptr addrspace(4) %5, align 4
+ %7 = inttoptr i32 %6 to ptr addrspace(3)
+ %8 = load i32, ptr addrspace(3) %7, align 4
+ %9 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %4, i32 %8
+ %10 = inttoptr i32 %3 to ptr addrspace(3)
+ %11 = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 1
+ %12 = load i32, ptr addrspace(4) %11, align 4
+ %13 = inttoptr i32 %12 to ptr addrspace(3)
+ %14 = load i32, ptr addrspace(3) %13, align 4
+ %15 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %10, i32 %14
+ store i8 3, ptr addrspace(3) %9, align 4
+ store i8 3, ptr addrspace(3) %15, align 8
+ ret void
+}
+
+define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0]] !llvm.amdgcn.lds.kernel.id [[META1:![0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP33:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i32 15
+; CHECK-NEXT: store i64 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr addrspace(4) [[TMP10]] to i64
+; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 3
+; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 2147450880
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
+; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP15]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP16]])
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[TMP17]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[ASAN_REPORT:%.*]], label [[TMP21:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP19:%.*]], label [[TMP20:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP11]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP20]]
+; CHECK: 20:
+; CHECK-NEXT: br label [[TMP21]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP24:%.*]] = udiv i64 [[TMP23]], 8
+; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP24]], 8
+; CHECK-NEXT: store i64 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP8]], [[TMP25]]
+; CHECK-NEXT: store i64 [[TMP26]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+; CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = udiv i64 [[TMP28]], 8
+; CHECK-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], 8
+; CHECK-NEXT: store i64 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP33]]
+; CHECK: 33:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP34]]
+; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP36]]
+; CHECK-NEXT: call void @use_variables()
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(3) [[TMP35]] to i64
+; CHECK-NEXT: [[TMP39:%.*]] = lshr i64 [[TMP38]], 3
+; CHECK-NEXT: [[TMP40:%.*]] = add i64 [[TMP39]], 2147450880
+; CHECK-NEXT: [[TMP41:%.*]] = inttoptr i64 [[TMP40]] to ptr
+; CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[TMP41]], align 1
+; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i8 [[TMP42]], 0
+; CHECK-NEXT: [[TMP44:%.*]] = and i64 [[TMP38]], 7
+; CHECK-NEXT: [[TMP45:%.*]] = trunc i64 [[TMP44]] to i8
+; CHECK-NEXT: [[TMP46:%.*]] = icmp sge i8 [[TMP45]], [[TMP42]]
+; CHECK-NEXT: [[TMP47:%.*]] = and i1 [[TMP43]], [[TMP46]]
+; CHECK-NEXT: [[TMP48:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP47]])
+; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[TMP48]], 0
+; CHECK-NEXT: br i1 [[TMP49]], label [[ASAN_REPORT1:%.*]], label [[TMP52:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP47]], label [[TMP50:%.*]], label [[TMP51:%.*]]
+; CHECK: 50:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP38]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP51]]
+; CHECK: 51:
+; CHECK-NEXT: br label [[TMP52]]
+; CHECK: 52:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 1
+; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
+; CHECK-NEXT: [[TMP54:%.*]] = add i64 [[TMP53]], 3
+; CHECK-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP56:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
+; CHECK-NEXT: [[TMP57:%.*]] = lshr i64 [[TMP56]], 3
+; CHECK-NEXT: [[TMP58:%.*]] = add i64 [[TMP57]], 2147450880
+; CHECK-NEXT: [[TMP59:%.*]] = inttoptr i64 [[TMP58]] to ptr
+; CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[TMP59]], align 1
+; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i8 [[TMP60]], 0
+; CHECK-NEXT: [[TMP62:%.*]] = and i64 [[TMP56]], 7
+; CHECK-NEXT: [[TMP63:%.*]] = trunc i64 [[TMP62]] to i8
+; CHECK-NEXT: [[TMP64:%.*]] = icmp sge i8 [[TMP63]], [[TMP60]]
+; CHECK-NEXT: [[TMP65:%.*]] = and i1 [[TMP61]], [[TMP64]]
+; CHECK-NEXT: [[TMP66:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP65]])
+; CHECK-NEXT: [[TMP67:%.*]] = icmp ne i64 [[TMP66]], 0
+; CHECK-NEXT: br i1 [[TMP67]], label [[ASAN_REPORT2:%.*]], label [[TMP70:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP65]], label [[TMP68:%.*]], label [[TMP69:%.*]]
+; CHECK: 68:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP56]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP69]]
+; CHECK: 69:
+; CHECK-NEXT: br label [[TMP70]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr addrspace(3) [[TMP55]] to i64
+; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP71]], 3
+; CHECK-NEXT: [[TMP73:%.*]] = add i64 [[TMP72]], 2147450880
+; CHECK-NEXT: [[TMP74:%.*]] = inttoptr i64 [[TMP73]] to ptr
+; CHECK-NEXT: [[TMP75:%.*]] = load i8, ptr [[TMP74]], align 1
+; CHECK-NEXT: [[TMP76:%.*]] = icmp ne i8 [[TMP75]], 0
+; CHECK-NEXT: [[TMP77:%.*]] = and i64 [[TMP71]], 7
+; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i8
+; CHECK-NEXT: [[TMP79:%.*]] = icmp sge i8 [[TMP78]], [[TMP75]]
+; CHECK-NEXT: [[TMP80:%.*]] = and i1 [[TMP76]], [[TMP79]]
+; CHECK-NEXT: [[TMP81:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP80]])
+; CHECK-NEXT: [[TMP82:%.*]] = icmp ne i64 [[TMP81]], 0
+; CHECK-NEXT: br i1 [[TMP82]], label [[ASAN_REPORT3:%.*]], label [[TMP85:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP80]], label [[TMP83:%.*]], label [[TMP84:%.*]]
+; CHECK: 83:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP71]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP84]]
+; CHECK: 84:
+; CHECK-NEXT: br label [[TMP85]]
+; CHECK: 85:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP37]], align 2
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP86:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP86]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %22
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %10 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %9, i32 15
+ store i64 %8, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+ %11 = load i64, ptr addrspace(4) %10, align 8
+ %12 = add i64 %11, 7
+ %13 = udiv i64 %12, 8
+ %14 = mul i64 %13, 8
+ store i64 %14, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+ %15 = add i64 %8, %14
+ store i64 %15, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+ %16 = load i64, ptr addrspace(4) %10, align 8
+ %17 = add i64 %16, 7
+ %18 = udiv i64 %17, 8
+ %19 = mul i64 %18, 8
+ store i64 %19, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+ %20 = add i64 %15, %19
+ %21 = call ptr addrspace(1) @malloc(i64 %20)
+ store ptr addrspace(1) %21, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %22
+
+22: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %23 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %24 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %23
+ %25 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+ %26 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %25
+ call void @use_variables()
+ store i8 7, ptr addrspace(3) %24, align 1
+ store i32 8, ptr addrspace(3) %26, align 2
+ br label %CondFree
+
+CondFree: ; preds = %22
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %27 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %27)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.lds.kernel.id() #0
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+
+!0 = !{i32 0}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+; CHECK: [[META1]] = !{i32 0}
+;.
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll
new file mode 100755
index 000000000000000..489185bdca04e24
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll
@@ -0,0 +1,400 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 24, i32 8 } }, no_sanitize_address
+ at llvm.amdgcn.sw.lds.base.table = internal addrspace(4) constant [1 x i32] [i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.sw.lds.k0 to i32)]
+ at llvm.amdgcn.sw.lds.offset.table = internal addrspace(4) constant [1 x [2 x i32]] [[2 x i32] [i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0) to i32), i32 ptrtoint (ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0) to i32)]]
+
+define void @use_variables() sanitize_address {
+; CHECK-LABEL: define void @use_variables(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr addrspace(4) [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 2147450880
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP3]], 7
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 3
+; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i8
+; CHECK-NEXT: [[TMP12:%.*]] = icmp sge i8 [[TMP11]], [[TMP7]]
+; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP8]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP13]])
+; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0
+; CHECK-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP13]], label [[TMP16:%.*]], label [[TMP17:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP3]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP17]]
+; CHECK: 17:
+; CHECK-NEXT: br label [[TMP18]]
+; CHECK: 18:
+; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(4) [[TMP21]] to i64
+; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP23]], 2147450880
+; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr
+; CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[TMP25]], align 1
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i8 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = and i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 3
+; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i8
+; CHECK-NEXT: [[TMP31:%.*]] = icmp sge i8 [[TMP30]], [[TMP26]]
+; CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP27]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP32]])
+; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i64 [[TMP33]], 0
+; CHECK-NEXT: br i1 [[TMP34]], label [[ASAN_REPORT1:%.*]], label [[TMP37:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP32]], label [[TMP35:%.*]], label [[TMP36:%.*]]
+; CHECK: 35:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP22]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP36]]
+; CHECK: 36:
+; CHECK-NEXT: br label [[TMP37]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(4) [[TMP21]], align 4
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
+; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
+; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
+; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
+; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
+; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
+; CHECK-NEXT: [[TMP47:%.*]] = add i64 [[TMP46]], 3
+; CHECK-NEXT: [[TMP48:%.*]] = trunc i64 [[TMP47]] to i8
+; CHECK-NEXT: [[TMP49:%.*]] = icmp sge i8 [[TMP48]], [[TMP44]]
+; CHECK-NEXT: [[TMP50:%.*]] = and i1 [[TMP45]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP50]])
+; CHECK-NEXT: [[TMP52:%.*]] = icmp ne i64 [[TMP51]], 0
+; CHECK-NEXT: br i1 [[TMP52]], label [[ASAN_REPORT2:%.*]], label [[TMP55:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP50]], label [[TMP53:%.*]], label [[TMP54:%.*]]
+; CHECK: 53:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP40]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP54]]
+; CHECK: 54:
+; CHECK-NEXT: br label [[TMP55]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(3) [[TMP39]], align 4
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP20]], i32 [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP19]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(4) [[TMP59]] to i64
+; CHECK-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP60]], 3
+; CHECK-NEXT: [[TMP62:%.*]] = add i64 [[TMP61]], 2147450880
+; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr
+; CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[TMP63]], align 1
+; CHECK-NEXT: [[TMP65:%.*]] = icmp ne i8 [[TMP64]], 0
+; CHECK-NEXT: [[TMP66:%.*]] = and i64 [[TMP60]], 7
+; CHECK-NEXT: [[TMP67:%.*]] = add i64 [[TMP66]], 3
+; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i8
+; CHECK-NEXT: [[TMP69:%.*]] = icmp sge i8 [[TMP68]], [[TMP64]]
+; CHECK-NEXT: [[TMP70:%.*]] = and i1 [[TMP65]], [[TMP69]]
+; CHECK-NEXT: [[TMP71:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP70]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i64 [[TMP71]], 0
+; CHECK-NEXT: br i1 [[TMP72]], label [[ASAN_REPORT3:%.*]], label [[TMP75:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP70]], label [[TMP73:%.*]], label [[TMP74:%.*]]
+; CHECK: 73:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP60]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 74:
+; CHECK-NEXT: br label [[TMP75]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(4) [[TMP59]], align 4
+; CHECK-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP78:%.*]] = ptrtoint ptr addrspace(3) [[TMP77]] to i64
+; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP78]], 3
+; CHECK-NEXT: [[TMP80:%.*]] = add i64 [[TMP79]], 2147450880
+; CHECK-NEXT: [[TMP81:%.*]] = inttoptr i64 [[TMP80]] to ptr
+; CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[TMP81]], align 1
+; CHECK-NEXT: [[TMP83:%.*]] = icmp ne i8 [[TMP82]], 0
+; CHECK-NEXT: [[TMP84:%.*]] = and i64 [[TMP78]], 7
+; CHECK-NEXT: [[TMP85:%.*]] = add i64 [[TMP84]], 3
+; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
+; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP82]]
+; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP83]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
+; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
+; CHECK-NEXT: br i1 [[TMP90]], label [[ASAN_REPORT4:%.*]], label [[TMP93:%.*]], !prof [[PROF0]]
+; CHECK: asan.report4:
+; CHECK-NEXT: br i1 [[TMP88]], label [[TMP91:%.*]], label [[TMP92:%.*]]
+; CHECK: 91:
+; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP78]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP92]]
+; CHECK: 92:
+; CHECK-NEXT: br label [[TMP93]]
+; CHECK: 93:
+; CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(3) [[TMP77]], align 4
+; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) [[TMP58]], i32 [[TMP94]]
+; CHECK-NEXT: [[X:%.*]] = addrspacecast ptr addrspace(3) [[TMP57]] to ptr
+; CHECK-NEXT: [[TMP96:%.*]] = addrspacecast ptr addrspace(3) [[TMP57]] to ptr
+; CHECK-NEXT: [[TMP97:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[TMP96]])
+; CHECK-NEXT: [[TMP98:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[TMP96]])
+; CHECK-NEXT: [[TMP99:%.*]] = or i1 [[TMP97]], [[TMP98]]
+; CHECK-NEXT: [[TMP100:%.*]] = xor i1 [[TMP99]], true
+; CHECK-NEXT: br i1 [[TMP100]], label [[TMP101:%.*]], label [[TMP117:%.*]]
+; CHECK: 101:
+; CHECK-NEXT: [[TMP102:%.*]] = ptrtoint ptr [[TMP96]] to i64
+; CHECK-NEXT: [[TMP103:%.*]] = lshr i64 [[TMP102]], 3
+; CHECK-NEXT: [[TMP104:%.*]] = add i64 [[TMP103]], 2147450880
+; CHECK-NEXT: [[TMP105:%.*]] = inttoptr i64 [[TMP104]] to ptr
+; CHECK-NEXT: [[TMP106:%.*]] = load i8, ptr [[TMP105]], align 1
+; CHECK-NEXT: [[TMP107:%.*]] = icmp ne i8 [[TMP106]], 0
+; CHECK-NEXT: [[TMP108:%.*]] = and i64 [[TMP102]], 7
+; CHECK-NEXT: [[TMP109:%.*]] = trunc i64 [[TMP108]] to i8
+; CHECK-NEXT: [[TMP110:%.*]] = icmp sge i8 [[TMP109]], [[TMP106]]
+; CHECK-NEXT: [[TMP111:%.*]] = and i1 [[TMP107]], [[TMP110]]
+; CHECK-NEXT: [[TMP112:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP111]])
+; CHECK-NEXT: [[TMP113:%.*]] = icmp ne i64 [[TMP112]], 0
+; CHECK-NEXT: br i1 [[TMP113]], label [[ASAN_REPORT5:%.*]], label [[TMP116:%.*]], !prof [[PROF0]]
+; CHECK: asan.report5:
+; CHECK-NEXT: br i1 [[TMP111]], label [[TMP114:%.*]], label [[TMP115:%.*]]
+; CHECK: 114:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP102]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP115]]
+; CHECK: 115:
+; CHECK-NEXT: br label [[TMP116]]
+; CHECK: 116:
+; CHECK-NEXT: br label [[TMP117]]
+; CHECK: 117:
+; CHECK-NEXT: store i8 3, ptr [[TMP96]], align 4
+; CHECK-NEXT: [[TMP118:%.*]] = ptrtoint ptr addrspace(3) [[TMP95]] to i64
+; CHECK-NEXT: [[TMP119:%.*]] = lshr i64 [[TMP118]], 3
+; CHECK-NEXT: [[TMP120:%.*]] = add i64 [[TMP119]], 2147450880
+; CHECK-NEXT: [[TMP121:%.*]] = inttoptr i64 [[TMP120]] to ptr
+; CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[TMP121]], align 1
+; CHECK-NEXT: [[TMP123:%.*]] = icmp ne i8 [[TMP122]], 0
+; CHECK-NEXT: [[TMP124:%.*]] = and i64 [[TMP118]], 7
+; CHECK-NEXT: [[TMP125:%.*]] = trunc i64 [[TMP124]] to i8
+; CHECK-NEXT: [[TMP126:%.*]] = icmp sge i8 [[TMP125]], [[TMP122]]
+; CHECK-NEXT: [[TMP127:%.*]] = and i1 [[TMP123]], [[TMP126]]
+; CHECK-NEXT: [[TMP128:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP127]])
+; CHECK-NEXT: [[TMP129:%.*]] = icmp ne i64 [[TMP128]], 0
+; CHECK-NEXT: br i1 [[TMP129]], label [[ASAN_REPORT6:%.*]], label [[TMP132:%.*]], !prof [[PROF0]]
+; CHECK: asan.report6:
+; CHECK-NEXT: br i1 [[TMP127]], label [[TMP130:%.*]], label [[TMP131:%.*]]
+; CHECK: 130:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP118]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP131]]
+; CHECK: 131:
+; CHECK-NEXT: br label [[TMP132]]
+; CHECK: 132:
+; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP95]], align 8
+; CHECK-NEXT: ret void
+;
+ %1 = call i32 @llvm.amdgcn.lds.kernel.id()
+ %2 = getelementptr inbounds [1 x i32], ptr addrspace(4) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 %1
+ %3 = load i32, ptr addrspace(4) %2, align 4
+ %4 = inttoptr i32 %3 to ptr addrspace(3)
+ %5 = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 0
+ %6 = load i32, ptr addrspace(4) %5, align 4
+ %7 = inttoptr i32 %6 to ptr addrspace(3)
+ %8 = load i32, ptr addrspace(3) %7, align 4
+ %9 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %4, i32 %8
+ %10 = inttoptr i32 %3 to ptr addrspace(3)
+ %11 = getelementptr inbounds [1 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 %1, i32 1
+ %12 = load i32, ptr addrspace(4) %11, align 4
+ %13 = inttoptr i32 %12 to ptr addrspace(3)
+ %14 = load i32, ptr addrspace(3) %13, align 4
+ %15 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %10, i32 %14
+ %X = addrspacecast ptr addrspace(3) %9 to ptr
+ %16 = addrspacecast ptr addrspace(3) %9 to ptr
+ store i8 3, ptr %16, align 4
+ store i8 3, ptr addrspace(3) %15, align 8
+ ret void
+}
+
+define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0]] !llvm.amdgcn.lds.kernel.id [[META1:![0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP10:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP8]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP9]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP13]]
+; CHECK-NEXT: call void @use_variables()
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr addrspace(3) [[TMP12]] to i64
+; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP15]], 3
+; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 2147450880
+; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
+; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[TMP18]], align 1
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i8 [[TMP19]], 0
+; CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP15]], 7
+; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i8
+; CHECK-NEXT: [[TMP23:%.*]] = icmp sge i8 [[TMP22]], [[TMP19]]
+; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
+; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
+; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
+; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
+; CHECK: 27:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP15]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP12]], align 1
+; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP14]] to i64
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 3
+; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr addrspace(3) [[TMP14]] to i64
+; CHECK-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP33]], 3
+; CHECK-NEXT: [[TMP35:%.*]] = add i64 [[TMP34]], 2147450880
+; CHECK-NEXT: [[TMP36:%.*]] = inttoptr i64 [[TMP35]] to ptr
+; CHECK-NEXT: [[TMP37:%.*]] = load i8, ptr [[TMP36]], align 1
+; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i8 [[TMP37]], 0
+; CHECK-NEXT: [[TMP39:%.*]] = and i64 [[TMP33]], 7
+; CHECK-NEXT: [[TMP40:%.*]] = trunc i64 [[TMP39]] to i8
+; CHECK-NEXT: [[TMP41:%.*]] = icmp sge i8 [[TMP40]], [[TMP37]]
+; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP38]], [[TMP41]]
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP42]])
+; CHECK-NEXT: [[TMP44:%.*]] = icmp ne i64 [[TMP43]], 0
+; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT1:%.*]], label [[TMP47:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP45:%.*]], label [[TMP46:%.*]]
+; CHECK: 45:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP33]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i64
+; CHECK-NEXT: [[TMP49:%.*]] = lshr i64 [[TMP48]], 3
+; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[TMP49]], 2147450880
+; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP50]] to ptr
+; CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[TMP51]], align 1
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i8 [[TMP52]], 0
+; CHECK-NEXT: [[TMP54:%.*]] = and i64 [[TMP48]], 7
+; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i8
+; CHECK-NEXT: [[TMP56:%.*]] = icmp sge i8 [[TMP55]], [[TMP52]]
+; CHECK-NEXT: [[TMP57:%.*]] = and i1 [[TMP53]], [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP57]])
+; CHECK-NEXT: [[TMP59:%.*]] = icmp ne i64 [[TMP58]], 0
+; CHECK-NEXT: br i1 [[TMP59]], label [[ASAN_REPORT2:%.*]], label [[TMP62:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP60:%.*]], label [[TMP61:%.*]]
+; CHECK: 60:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP48]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP14]], align 2
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP63:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP63]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %10
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(1) @malloc(i64 %8)
+ store ptr addrspace(1) %9, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %10
+
+10: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %11 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %12 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %11
+ %13 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+ %14 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %13
+ call void @use_variables()
+ store i8 7, ptr addrspace(3) %12, align 1
+ store i32 8, ptr addrspace(3) %14, align 2
+ br label %CondFree
+
+CondFree: ; preds = %10
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %15 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %15)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.lds.kernel.id() #0
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+
+!0 = !{i32 0}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+; CHECK: [[META1]] = !{i32 0}
+;.
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll
new file mode 100755
index 000000000000000..cfc5031331f9fcc
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll
@@ -0,0 +1,262 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 0 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 0 } }, no_sanitize_address
+
+define amdgpu_kernel void @k0() sanitize_address {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP33:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i32 15
+; CHECK-NEXT: store i64 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr addrspace(4) [[TMP10]] to i64
+; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 3
+; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 2147450880
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
+; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP15]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP16]])
+; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i64 [[TMP17]], 0
+; CHECK-NEXT: br i1 [[TMP18]], label [[ASAN_REPORT:%.*]], label [[TMP21:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP16]], label [[TMP19:%.*]], label [[TMP20:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP11]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP20]]
+; CHECK: 20:
+; CHECK-NEXT: br label [[TMP21]]
+; CHECK: 21:
+; CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 7
+; CHECK-NEXT: [[TMP24:%.*]] = udiv i64 [[TMP23]], 8
+; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP24]], 8
+; CHECK-NEXT: store i64 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP8]], [[TMP25]]
+; CHECK-NEXT: store i64 [[TMP26]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+; CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(4) [[TMP10]], align 8
+; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 7
+; CHECK-NEXT: [[TMP29:%.*]] = udiv i64 [[TMP28]], 8
+; CHECK-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], 8
+; CHECK-NEXT: store i64 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP33]]
+; CHECK: 33:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP34]]
+; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP36]]
+; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP38]]
+; CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP40]]
+; CHECK-NEXT: [[TMP42:%.*]] = ptrtoint ptr addrspace(3) [[TMP35]] to i64
+; CHECK-NEXT: [[TMP43:%.*]] = lshr i64 [[TMP42]], 3
+; CHECK-NEXT: [[TMP44:%.*]] = add i64 [[TMP43]], 2147450880
+; CHECK-NEXT: [[TMP45:%.*]] = inttoptr i64 [[TMP44]] to ptr
+; CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[TMP45]], align 1
+; CHECK-NEXT: [[TMP47:%.*]] = icmp ne i8 [[TMP46]], 0
+; CHECK-NEXT: [[TMP48:%.*]] = and i64 [[TMP42]], 7
+; CHECK-NEXT: [[TMP49:%.*]] = trunc i64 [[TMP48]] to i8
+; CHECK-NEXT: [[TMP50:%.*]] = icmp sge i8 [[TMP49]], [[TMP46]]
+; CHECK-NEXT: [[TMP51:%.*]] = and i1 [[TMP47]], [[TMP50]]
+; CHECK-NEXT: [[TMP52:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP51]])
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i64 [[TMP52]], 0
+; CHECK-NEXT: br i1 [[TMP53]], label [[ASAN_REPORT1:%.*]], label [[TMP56:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP51]], label [[TMP54:%.*]], label [[TMP55:%.*]]
+; CHECK: 54:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP42]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP55]]
+; CHECK: 55:
+; CHECK-NEXT: br label [[TMP56]]
+; CHECK: 56:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 4
+; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
+; CHECK-NEXT: [[TMP58:%.*]] = lshr i64 [[TMP57]], 3
+; CHECK-NEXT: [[TMP59:%.*]] = add i64 [[TMP58]], 2147450880
+; CHECK-NEXT: [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr
+; CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[TMP60]], align 1
+; CHECK-NEXT: [[TMP62:%.*]] = icmp ne i8 [[TMP61]], 0
+; CHECK-NEXT: [[TMP63:%.*]] = and i64 [[TMP57]], 7
+; CHECK-NEXT: [[TMP64:%.*]] = add i64 [[TMP63]], 3
+; CHECK-NEXT: [[TMP65:%.*]] = trunc i64 [[TMP64]] to i8
+; CHECK-NEXT: [[TMP66:%.*]] = icmp sge i8 [[TMP65]], [[TMP61]]
+; CHECK-NEXT: [[TMP67:%.*]] = and i1 [[TMP62]], [[TMP66]]
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP67]])
+; CHECK-NEXT: [[TMP69:%.*]] = icmp ne i64 [[TMP68]], 0
+; CHECK-NEXT: br i1 [[TMP69]], label [[ASAN_REPORT2:%.*]], label [[TMP72:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP67]], label [[TMP70:%.*]], label [[TMP71:%.*]]
+; CHECK: 70:
+; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP57]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP71]]
+; CHECK: 71:
+; CHECK-NEXT: br label [[TMP72]]
+; CHECK: 72:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP37]], align 8
+; CHECK-NEXT: [[TMP73:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
+; CHECK-NEXT: [[TMP74:%.*]] = lshr i64 [[TMP73]], 3
+; CHECK-NEXT: [[TMP75:%.*]] = add i64 [[TMP74]], 2147450880
+; CHECK-NEXT: [[TMP76:%.*]] = inttoptr i64 [[TMP75]] to ptr
+; CHECK-NEXT: [[TMP77:%.*]] = load i8, ptr [[TMP76]], align 1
+; CHECK-NEXT: [[TMP78:%.*]] = icmp ne i8 [[TMP77]], 0
+; CHECK-NEXT: [[TMP79:%.*]] = and i64 [[TMP73]], 7
+; CHECK-NEXT: [[TMP80:%.*]] = trunc i64 [[TMP79]] to i8
+; CHECK-NEXT: [[TMP81:%.*]] = icmp sge i8 [[TMP80]], [[TMP77]]
+; CHECK-NEXT: [[TMP82:%.*]] = and i1 [[TMP78]], [[TMP81]]
+; CHECK-NEXT: [[TMP83:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP82]])
+; CHECK-NEXT: [[TMP84:%.*]] = icmp ne i64 [[TMP83]], 0
+; CHECK-NEXT: br i1 [[TMP84]], label [[ASAN_REPORT3:%.*]], label [[TMP87:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
+; CHECK-NEXT: br i1 [[TMP82]], label [[TMP85:%.*]], label [[TMP86:%.*]]
+; CHECK: 85:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP73]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP86]]
+; CHECK: 86:
+; CHECK-NEXT: br label [[TMP87]]
+; CHECK: 87:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP39]], align 4
+; CHECK-NEXT: [[TMP88:%.*]] = ptrtoint ptr addrspace(3) [[TMP41]] to i64
+; CHECK-NEXT: [[TMP89:%.*]] = lshr i64 [[TMP88]], 3
+; CHECK-NEXT: [[TMP90:%.*]] = add i64 [[TMP89]], 2147450880
+; CHECK-NEXT: [[TMP91:%.*]] = inttoptr i64 [[TMP90]] to ptr
+; CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[TMP91]], align 1
+; CHECK-NEXT: [[TMP93:%.*]] = icmp ne i8 [[TMP92]], 0
+; CHECK-NEXT: [[TMP94:%.*]] = and i64 [[TMP88]], 7
+; CHECK-NEXT: [[TMP95:%.*]] = trunc i64 [[TMP94]] to i8
+; CHECK-NEXT: [[TMP96:%.*]] = icmp sge i8 [[TMP95]], [[TMP92]]
+; CHECK-NEXT: [[TMP97:%.*]] = and i1 [[TMP93]], [[TMP96]]
+; CHECK-NEXT: [[TMP98:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP97]])
+; CHECK-NEXT: [[TMP99:%.*]] = icmp ne i64 [[TMP98]], 0
+; CHECK-NEXT: br i1 [[TMP99]], label [[ASAN_REPORT4:%.*]], label [[TMP102:%.*]], !prof [[PROF0]]
+; CHECK: asan.report4:
+; CHECK-NEXT: br i1 [[TMP97]], label [[TMP100:%.*]], label [[TMP101:%.*]]
+; CHECK: 100:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP88]]) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP101]]
+; CHECK: 101:
+; CHECK-NEXT: br label [[TMP102]]
+; CHECK: 102:
+; CHECK-NEXT: store i8 8, ptr addrspace(3) [[TMP41]], align 8
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP103:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP103]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %22
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %10 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %9, i32 15
+ store i64 %8, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 8
+ %11 = load i64, ptr addrspace(4) %10, align 8
+ %12 = add i64 %11, 7
+ %13 = udiv i64 %12, 8
+ %14 = mul i64 %13, 8
+ store i64 %14, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 8
+ %15 = add i64 %8, %14
+ store i64 %15, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 8
+ %16 = load i64, ptr addrspace(4) %10, align 8
+ %17 = add i64 %16, 7
+ %18 = udiv i64 %17, 8
+ %19 = mul i64 %18, 8
+ store i64 %19, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 8
+ %20 = add i64 %15, %19
+ %21 = call ptr addrspace(1) @malloc(i64 %20)
+ store ptr addrspace(1) %21, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %22
+
+22: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %23 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %24 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %23
+ %25 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+ %26 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %25
+ %27 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
+ %28 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %27
+ %29 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+ %30 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %29
+ store i8 7, ptr addrspace(3) %24, align 4
+ store i32 8, ptr addrspace(3) %26, align 8
+ store i8 7, ptr addrspace(3) %28, align 4
+ store i8 8, ptr addrspace(3) %30, align 8
+ br label %CondFree
+
+CondFree: ; preds = %22
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %31 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %31)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+;.
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll
new file mode 100755
index 000000000000000..bdf86bb53781f05
--- /dev/null
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll
@@ -0,0 +1,177 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=asan -S -mtriple=amdgcn-- | FileCheck %s
+
+%llvm.amdgcn.sw.lds.k0.md.type = type { %llvm.amdgcn.sw.lds.k0.md.item, %llvm.amdgcn.sw.lds.k0.md.item }
+%llvm.amdgcn.sw.lds.k0.md.item = type { i32, i32 }
+ at llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8
+ at llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 8 } }, no_sanitize_address
+
+define amdgpu_kernel void @k0() sanitize_address {
+; CHECK-LABEL: define amdgpu_kernel void @k0(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: WId:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP10:%.*]]
+; CHECK: Malloc:
+; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP8]])
+; CHECK-NEXT: store ptr addrspace(1) [[TMP9]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: br label [[TMP10]]
+; CHECK: 10:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP13]]
+; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr addrspace(3) [[TMP12]] to i64
+; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP15]], 3
+; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 2147450880
+; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
+; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[TMP18]], align 1
+; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i8 [[TMP19]], 0
+; CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP15]], 7
+; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i8
+; CHECK-NEXT: [[TMP23:%.*]] = icmp sge i8 [[TMP22]], [[TMP19]]
+; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
+; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
+; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
+; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
+; CHECK: 27:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP15]]) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP28]]
+; CHECK: 28:
+; CHECK-NEXT: br label [[TMP29]]
+; CHECK: 29:
+; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP12]], align 4
+; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP14]] to i64
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 3
+; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr addrspace(3)
+; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr addrspace(3) [[TMP14]] to i64
+; CHECK-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP33]], 3
+; CHECK-NEXT: [[TMP35:%.*]] = add i64 [[TMP34]], 2147450880
+; CHECK-NEXT: [[TMP36:%.*]] = inttoptr i64 [[TMP35]] to ptr
+; CHECK-NEXT: [[TMP37:%.*]] = load i8, ptr [[TMP36]], align 1
+; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i8 [[TMP37]], 0
+; CHECK-NEXT: [[TMP39:%.*]] = and i64 [[TMP33]], 7
+; CHECK-NEXT: [[TMP40:%.*]] = trunc i64 [[TMP39]] to i8
+; CHECK-NEXT: [[TMP41:%.*]] = icmp sge i8 [[TMP40]], [[TMP37]]
+; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP38]], [[TMP41]]
+; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP42]])
+; CHECK-NEXT: [[TMP44:%.*]] = icmp ne i64 [[TMP43]], 0
+; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT1:%.*]], label [[TMP47:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP42]], label [[TMP45:%.*]], label [[TMP46:%.*]]
+; CHECK: 45:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP33]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP46]]
+; CHECK: 46:
+; CHECK-NEXT: br label [[TMP47]]
+; CHECK: 47:
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i64
+; CHECK-NEXT: [[TMP49:%.*]] = lshr i64 [[TMP48]], 3
+; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[TMP49]], 2147450880
+; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP50]] to ptr
+; CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[TMP51]], align 1
+; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i8 [[TMP52]], 0
+; CHECK-NEXT: [[TMP54:%.*]] = and i64 [[TMP48]], 7
+; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i8
+; CHECK-NEXT: [[TMP56:%.*]] = icmp sge i8 [[TMP55]], [[TMP52]]
+; CHECK-NEXT: [[TMP57:%.*]] = and i1 [[TMP53]], [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP57]])
+; CHECK-NEXT: [[TMP59:%.*]] = icmp ne i64 [[TMP58]], 0
+; CHECK-NEXT: br i1 [[TMP59]], label [[ASAN_REPORT2:%.*]], label [[TMP62:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP57]], label [[TMP60:%.*]], label [[TMP61:%.*]]
+; CHECK: 60:
+; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP48]], i64 4) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP61]]
+; CHECK: 61:
+; CHECK-NEXT: br label [[TMP62]]
+; CHECK: 62:
+; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP14]], align 2
+; CHECK-NEXT: br label [[CONDFREE:%.*]]
+; CHECK: CondFree:
+; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
+; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
+; CHECK: Free:
+; CHECK-NEXT: [[TMP63:%.*]] = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: call void @free(ptr [[TMP63]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: End:
+; CHECK-NEXT: ret void
+;
+WId:
+ %0 = call i32 @llvm.amdgcn.workitem.id.x()
+ %1 = call i32 @llvm.amdgcn.workitem.id.y()
+ %2 = call i32 @llvm.amdgcn.workitem.id.z()
+ %3 = or i32 %0, %1
+ %4 = or i32 %3, %2
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %Malloc, label %10
+
+Malloc: ; preds = %WId
+ %6 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 8
+ %7 = load i64, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 8
+ %8 = add i64 %6, %7
+ %9 = call ptr addrspace(1) @malloc(i64 %8)
+ store ptr addrspace(1) %9, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ br label %10
+
+10: ; preds = %Malloc, %WId
+ %xyzCond = phi i1 [ false, %WId ], [ true, %Malloc ]
+ call void @llvm.amdgcn.s.barrier()
+ %11 = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
+ %12 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %11
+ %13 = load i32, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+ %14 = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 %13
+ store i8 7, ptr addrspace(3) %12, align 4
+ store i32 8, ptr addrspace(3) %14, align 2
+ br label %CondFree
+
+CondFree: ; preds = %10
+ call void @llvm.amdgcn.s.barrier()
+ br i1 %xyzCond, label %Free, label %End
+
+Free: ; preds = %CondFree
+ %15 = load ptr, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+ call void @free(ptr %15)
+ br label %End
+
+End: ; preds = %Free, %CondFree
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.y() #0
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.workitem.id.z() #0
+
+declare ptr addrspace(1) @malloc(i64)
+
+; Function Attrs: convergent nocallback nofree nounwind willreturn
+declare void @llvm.amdgcn.s.barrier() #1
+
+declare void @free(ptr)
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nofree nounwind willreturn }
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 100000}
+;.
>From fe15d89914845f40c03327babd7cba645aa3442b Mon Sep 17 00:00:00 2001
From: skc7 <Krishna.Sankisa at amd.com>
Date: Wed, 17 Apr 2024 21:51:46 +0530
Subject: [PATCH 2/2] [AMDGPU] Call __asan_poison_region for poisoning redzones
---
.../Instrumentation/AddressSanitizer.cpp | 70 +++++++++++++++++-
.../asan-instr-lds-dynamic-indirect-access.ll | 30 +++++---
...ds-multi-static-dynamic-indirect-access.ll | 31 +++++---
...nstr-lds-static-dynamic-indirect-access.ll | 30 +++++---
.../asan-instr-lds-static-indirect-access.ll | 71 ++++++++++++++-----
.../asan-instr-static-dynamic-lds-test.ll | 36 ++++++----
.../AMDGPU/asan-instr-static-lds-test.ll | 63 +++++++++++-----
7 files changed, 254 insertions(+), 77 deletions(-)
diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index 6067b996c42d6ba..a24f26eada3b0a5 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -1396,9 +1396,77 @@ static void UpdateSwLDSMetadataWithRedzoneInfo(Function &F, int Scale) {
return;
}
+static void poisonRedzonesForSwLDS(Function& F) {
+ Module *M = F.getParent();
+ GlobalVariable *SwLDSGlobal = getKernelSwLDSGlobal(*M, F);
+ GlobalVariable *SwLDSMetadataGlobal = getKernelSwLDSMetadataGlobal(*M, F);
+
+ if (!SwLDSGlobal || !SwLDSMetadataGlobal) return;
+
+ LLVMContext &Ctx = M->getContext();
+ Type *Int64Ty = Type::getInt64Ty(Ctx);
+ Type *VoidTy = Type::getVoidTy(Ctx);
+ FunctionCallee AsanPoisonRegion = M->getOrInsertFunction(
+ StringRef("__asan_poison_region"),
+ FunctionType::get(VoidTy,
+ {Int64Ty, Int64Ty}, false));
+ Constant *MdInit = SwLDSMetadataGlobal->getInitializer();
+
+ for (User *U : SwLDSGlobal->users()) {
+ StoreInst *SI = dyn_cast<StoreInst>(U);
+ if (!SI) continue;
+
+ // Check if the value being stored is the result of a malloc
+ CallInst *CI = dyn_cast<CallInst>(SI->getValueOperand());
+ if (!CI) continue;
+
+ Function *F = CI->getCalledFunction();
+ if (!F && !(F->getName() == "malloc"))
+ continue;
+
+ StructType *MDStructType =
+ cast<StructType>(SwLDSMetadataGlobal->getValueType());
+ assert(MDStructType);
+ unsigned NumStructs = MDStructType->getNumElements();
+ Value* StoreMallocPointer = SI->getValueOperand();
+
+ for (unsigned i = 0; i < NumStructs; i++) {
+ ConstantStruct *member = dyn_cast<ConstantStruct>(MdInit->getAggregateElement(i));
+ if (!member) continue;
+
+ ConstantInt *GlobalSize =
+ cast<ConstantInt>(member->getAggregateElement(1U));
+ unsigned GlobalSizeValue = GlobalSize->getZExtValue();
+
+ if (!GlobalSizeValue) continue;
+ IRBuilder<> IRB(SI);
+ IRB.SetInsertPoint(SI->getNextNode());
+
+ auto *GEPForOffset = IRB.CreateInBoundsGEP(
+ MDStructType, SwLDSMetadataGlobal,
+ {IRB.getInt32(0), IRB.getInt32(i), IRB.getInt32(2)});
+
+ auto *GEPForSize = IRB.CreateInBoundsGEP(
+ MDStructType, SwLDSMetadataGlobal,
+ {IRB.getInt32(0), IRB.getInt32(i), IRB.getInt32(3)});
+
+ Value *RedzoneOffset =
+ IRB.CreateLoad(IRB.getInt64Ty(), GEPForOffset);
+ Value* RedzoneAddrOffset = IRB.CreateInBoundsGEP(
+ IRB.getInt8Ty(), StoreMallocPointer, {RedzoneOffset});
+ Value* RedzoneAddress = IRB.CreatePtrToInt(RedzoneAddrOffset, IRB.getInt64Ty());
+ Value *Redzonesize = IRB.CreateLoad(IRB.getInt64Ty(), GEPForSize);
+ IRB.CreateCall(AsanPoisonRegion, {RedzoneAddress, Redzonesize});
+ }
+ }
+ return;
+}
+
static void preProcessAMDGPULDSAccesses(Module &M, int Scale) {
- for (Function &F : M)
+ for (Function &F : M) {
UpdateSwLDSMetadataWithRedzoneInfo(F, Scale);
+ poisonRedzonesForSwLDS(F);
+ }
return;
}
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll
index 31dc4da9a9d6bd8..d22583f5b3c2afc 100755
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-dynamic-indirect-access.ll
@@ -260,8 +260,18 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP87:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 8
+; CHECK-NEXT: [[TMP88:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = ptrtoint ptr addrspace(1) [[TMP88]] to i64
+; CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP89]], i64 [[TMP90]])
+; CHECK-NEXT: [[TMP91:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr addrspace(1) [[TMP92]] to i64
+; CHECK-NEXT: [[TMP94:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP93]], i64 [[TMP94]])
; CHECK-NEXT: br label [[TMP33]]
-; CHECK: 33:
+; CHECK: 41:
; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
@@ -284,13 +294,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP49]], label [[ASAN_REPORT1:%.*]], label [[TMP52:%.*]], !prof [[PROF0]]
; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP47]], label [[TMP50:%.*]], label [[TMP51:%.*]]
-; CHECK: 50:
+; CHECK: 58:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP38]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP51]]
-; CHECK: 51:
+; CHECK: 59:
; CHECK-NEXT: br label [[TMP52]]
-; CHECK: 52:
+; CHECK: 60:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 1
; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
; CHECK-NEXT: [[TMP54:%.*]] = add i64 [[TMP53]], 3
@@ -310,13 +320,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP67]], label [[ASAN_REPORT2:%.*]], label [[TMP70:%.*]], !prof [[PROF0]]
; CHECK: asan.report2:
; CHECK-NEXT: br i1 [[TMP65]], label [[TMP68:%.*]], label [[TMP69:%.*]]
-; CHECK: 68:
+; CHECK: 76:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP56]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP69]]
-; CHECK: 69:
+; CHECK: 77:
; CHECK-NEXT: br label [[TMP70]]
-; CHECK: 70:
+; CHECK: 78:
; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr addrspace(3) [[TMP55]] to i64
; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP71]], 3
; CHECK-NEXT: [[TMP73:%.*]] = add i64 [[TMP72]], 2147450880
@@ -332,13 +342,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP82]], label [[ASAN_REPORT3:%.*]], label [[TMP85:%.*]], !prof [[PROF0]]
; CHECK: asan.report3:
; CHECK-NEXT: br i1 [[TMP80]], label [[TMP83:%.*]], label [[TMP84:%.*]]
-; CHECK: 83:
+; CHECK: 91:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP71]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP84]]
-; CHECK: 84:
+; CHECK: 92:
; CHECK-NEXT: br label [[TMP85]]
-; CHECK: 85:
+; CHECK: 93:
; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP37]], align 2
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll
index dac53c55725aafa..9297525763e8db4 100755
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-multi-static-dynamic-indirect-access.ll
@@ -490,8 +490,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP52]]
+; CHECK-NEXT: [[TMP54:%.*]] = ptrtoint ptr addrspace(1) [[TMP53]] to i64
+; CHECK-NEXT: [[TMP55:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP54]], i64 [[TMP55]])
; CHECK-NEXT: br label [[TMP33]]
-; CHECK: 33:
+; CHECK: 37:
; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
@@ -512,13 +517,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP47]], label [[ASAN_REPORT1:%.*]], label [[TMP50:%.*]], !prof [[PROF0]]
; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP45]], label [[TMP48:%.*]], label [[TMP49:%.*]]
-; CHECK: 48:
+; CHECK: 52:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP36]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP49]]
-; CHECK: 49:
+; CHECK: 53:
; CHECK-NEXT: br label [[TMP50]]
-; CHECK: 50:
+; CHECK: 54:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 1
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
@@ -644,8 +649,18 @@ define amdgpu_kernel void @k1() sanitize_address !llvm.amdgcn.lds.kernel.id !1 {
; CHECK-NEXT: [[TMP36:%.*]] = add i64 [[TMP31]], [[TMP35]]
; CHECK-NEXT: [[TMP37:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP36]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP37]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k1, align 8
+; CHECK-NEXT: [[TMP59:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 2), align 8
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP37]], i64 [[TMP59]]
+; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr addrspace(1) [[TMP60]] to i64
+; CHECK-NEXT: [[TMP62:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP61]], i64 [[TMP62]])
+; CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP37]], i64 [[TMP63]]
+; CHECK-NEXT: [[TMP65:%.*]] = ptrtoint ptr addrspace(1) [[TMP64]] to i64
+; CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP65]], i64 [[TMP66]])
; CHECK-NEXT: br label [[TMP38]]
-; CHECK: 38:
+; CHECK: 46:
; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[TMP2]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
@@ -669,13 +684,13 @@ define amdgpu_kernel void @k1() sanitize_address !llvm.amdgcn.lds.kernel.id !1 {
; CHECK-NEXT: br i1 [[TMP54]], label [[ASAN_REPORT1:%.*]], label [[TMP57:%.*]], !prof [[PROF0]]
; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP52]], label [[TMP55:%.*]], label [[TMP56:%.*]]
-; CHECK: 55:
+; CHECK: 63:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP43]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP56]]
-; CHECK: 56:
+; CHECK: 64:
; CHECK-NEXT: br label [[TMP57]]
-; CHECK: 57:
+; CHECK: 65:
; CHECK-NEXT: store i8 3, ptr addrspace(3) [[TMP40]], align 4
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll
index 31dc4da9a9d6bd8..d22583f5b3c2afc 100755
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-dynamic-indirect-access.ll
@@ -260,8 +260,18 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP87:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 8
+; CHECK-NEXT: [[TMP88:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = ptrtoint ptr addrspace(1) [[TMP88]] to i64
+; CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP89]], i64 [[TMP90]])
+; CHECK-NEXT: [[TMP91:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP91]]
+; CHECK-NEXT: [[TMP93:%.*]] = ptrtoint ptr addrspace(1) [[TMP92]] to i64
+; CHECK-NEXT: [[TMP94:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP93]], i64 [[TMP94]])
; CHECK-NEXT: br label [[TMP33]]
-; CHECK: 33:
+; CHECK: 41:
; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
@@ -284,13 +294,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP49]], label [[ASAN_REPORT1:%.*]], label [[TMP52:%.*]], !prof [[PROF0]]
; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP47]], label [[TMP50:%.*]], label [[TMP51:%.*]]
-; CHECK: 50:
+; CHECK: 58:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP38]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP51]]
-; CHECK: 51:
+; CHECK: 59:
; CHECK-NEXT: br label [[TMP52]]
-; CHECK: 52:
+; CHECK: 60:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 1
; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
; CHECK-NEXT: [[TMP54:%.*]] = add i64 [[TMP53]], 3
@@ -310,13 +320,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP67]], label [[ASAN_REPORT2:%.*]], label [[TMP70:%.*]], !prof [[PROF0]]
; CHECK: asan.report2:
; CHECK-NEXT: br i1 [[TMP65]], label [[TMP68:%.*]], label [[TMP69:%.*]]
-; CHECK: 68:
+; CHECK: 76:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP56]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP69]]
-; CHECK: 69:
+; CHECK: 77:
; CHECK-NEXT: br label [[TMP70]]
-; CHECK: 70:
+; CHECK: 78:
; CHECK-NEXT: [[TMP71:%.*]] = ptrtoint ptr addrspace(3) [[TMP55]] to i64
; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP71]], 3
; CHECK-NEXT: [[TMP73:%.*]] = add i64 [[TMP72]], 2147450880
@@ -332,13 +342,13 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: br i1 [[TMP82]], label [[ASAN_REPORT3:%.*]], label [[TMP85:%.*]], !prof [[PROF0]]
; CHECK: asan.report3:
; CHECK-NEXT: br i1 [[TMP80]], label [[TMP83:%.*]], label [[TMP84:%.*]]
-; CHECK: 83:
+; CHECK: 91:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP71]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP84]]
-; CHECK: 84:
+; CHECK: 92:
; CHECK-NEXT: br label [[TMP85]]
-; CHECK: 85:
+; CHECK: 93:
; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP37]], align 2
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll
index 489185bdca04e24..0b8b774a0bd4a6e 100755
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-lds-static-indirect-access.ll
@@ -238,9 +238,46 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP8]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP9]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 8
+; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP9]], i64 [[TMP64]]
+; CHECK-NEXT: [[TMP66:%.*]] = ptrtoint ptr addrspace(1) [[TMP65]] to i64
+; CHECK-NEXT: [[TMP67:%.*]] = lshr i64 ptrtoint (ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 3) to i64), 3
+; CHECK-NEXT: [[TMP68:%.*]] = add i64 [[TMP67]], 2147450880
+; CHECK-NEXT: [[TMP69:%.*]] = inttoptr i64 [[TMP68]] to ptr
+; CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[TMP69]], align 1
+; CHECK-NEXT: [[TMP71:%.*]] = icmp ne i8 [[TMP70]], 0
+; CHECK-NEXT: [[TMP72:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP71]])
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[TMP72]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[ASAN_REPORT:%.*]], label [[TMP74:%.*]], !prof [[PROF0]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP71]], label [[TMP75:%.*]], label [[TMP76:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: call void @__asan_report_load8(i64 ptrtoint (ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 3) to i64)) #[[ATTR6]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP76]]
+; CHECK: 21:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP77:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP66]], i64 [[TMP77]])
+; CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 8
+; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP9]], i64 [[TMP78]]
+; CHECK-NEXT: [[TMP80:%.*]] = ptrtoint ptr addrspace(1) [[TMP79]] to i64
+; CHECK-NEXT: [[TMP81:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP80]], i64 [[TMP81]])
+; CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 8
+; CHECK-NEXT: [[TMP83:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP9]], i64 [[TMP82]]
+; CHECK-NEXT: [[TMP84:%.*]] = ptrtoint ptr addrspace(1) [[TMP83]] to i64
+; CHECK-NEXT: [[TMP85:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP84]], i64 [[TMP85]])
+; CHECK-NEXT: [[TMP86:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP87:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP9]], i64 [[TMP86]]
+; CHECK-NEXT: [[TMP88:%.*]] = ptrtoint ptr addrspace(1) [[TMP87]] to i64
+; CHECK-NEXT: [[TMP89:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP88]], i64 [[TMP89]])
; CHECK-NEXT: br label [[TMP10]]
-; CHECK: 10:
-; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]
+; CHECK: 36:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP74]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP11]]
@@ -259,16 +296,16 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF0]]
-; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT1:%.*]], label [[TMP29:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
+; CHECK: 53:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP15]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
+; CHECK: 54:
; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK: 55:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP12]], align 1
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP14]] to i64
; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 3
@@ -285,16 +322,16 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP38]], [[TMP41]]
; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP42]])
; CHECK-NEXT: [[TMP44:%.*]] = icmp ne i64 [[TMP43]], 0
-; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT1:%.*]], label [[TMP47:%.*]], !prof [[PROF0]]
-; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT2:%.*]], label [[TMP47:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
; CHECK-NEXT: br i1 [[TMP42]], label [[TMP45:%.*]], label [[TMP46:%.*]]
-; CHECK: 45:
+; CHECK: 71:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP33]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 46:
+; CHECK: 72:
; CHECK-NEXT: br label [[TMP47]]
-; CHECK: 47:
+; CHECK: 73:
; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i64
; CHECK-NEXT: [[TMP49:%.*]] = lshr i64 [[TMP48]], 3
; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[TMP49]], 2147450880
@@ -307,16 +344,16 @@ define amdgpu_kernel void @k0() sanitize_address !llvm.amdgcn.lds.kernel.id !0 {
; CHECK-NEXT: [[TMP57:%.*]] = and i1 [[TMP53]], [[TMP56]]
; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP57]])
; CHECK-NEXT: [[TMP59:%.*]] = icmp ne i64 [[TMP58]], 0
-; CHECK-NEXT: br i1 [[TMP59]], label [[ASAN_REPORT2:%.*]], label [[TMP62:%.*]], !prof [[PROF0]]
-; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP59]], label [[ASAN_REPORT3:%.*]], label [[TMP62:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
; CHECK-NEXT: br i1 [[TMP57]], label [[TMP60:%.*]], label [[TMP61:%.*]]
-; CHECK: 60:
+; CHECK: 86:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP48]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP61]]
-; CHECK: 61:
+; CHECK: 87:
; CHECK-NEXT: br label [[TMP62]]
-; CHECK: 62:
+; CHECK: 88:
; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP14]], align 2
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll
index cfc5031331f9fcc..18efc42962f469b 100755
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-dynamic-lds-test.ll
@@ -57,8 +57,18 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP26]], [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP31]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP32]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 8
+; CHECK-NEXT: [[TMP105:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = ptrtoint ptr addrspace(1) [[TMP105]] to i64
+; CHECK-NEXT: [[TMP107:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP106]], i64 [[TMP107]])
+; CHECK-NEXT: [[TMP108:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP109:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP32]], i64 [[TMP108]]
+; CHECK-NEXT: [[TMP110:%.*]] = ptrtoint ptr addrspace(1) [[TMP109]] to i64
+; CHECK-NEXT: [[TMP111:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP110]], i64 [[TMP111]])
; CHECK-NEXT: br label [[TMP33]]
-; CHECK: 33:
+; CHECK: 41:
; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP21]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
@@ -84,13 +94,13 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: br i1 [[TMP53]], label [[ASAN_REPORT1:%.*]], label [[TMP56:%.*]], !prof [[PROF0]]
; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP51]], label [[TMP54:%.*]], label [[TMP55:%.*]]
-; CHECK: 54:
+; CHECK: 62:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP42]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP55]]
-; CHECK: 55:
+; CHECK: 63:
; CHECK-NEXT: br label [[TMP56]]
-; CHECK: 56:
+; CHECK: 64:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP35]], align 4
; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr addrspace(3) [[TMP37]] to i64
; CHECK-NEXT: [[TMP58:%.*]] = lshr i64 [[TMP57]], 3
@@ -108,13 +118,13 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: br i1 [[TMP69]], label [[ASAN_REPORT2:%.*]], label [[TMP72:%.*]], !prof [[PROF0]]
; CHECK: asan.report2:
; CHECK-NEXT: br i1 [[TMP67]], label [[TMP70:%.*]], label [[TMP71:%.*]]
-; CHECK: 70:
+; CHECK: 78:
; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP57]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP71]]
-; CHECK: 71:
+; CHECK: 79:
; CHECK-NEXT: br label [[TMP72]]
-; CHECK: 72:
+; CHECK: 80:
; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP37]], align 8
; CHECK-NEXT: [[TMP73:%.*]] = ptrtoint ptr addrspace(3) [[TMP39]] to i64
; CHECK-NEXT: [[TMP74:%.*]] = lshr i64 [[TMP73]], 3
@@ -131,13 +141,13 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: br i1 [[TMP84]], label [[ASAN_REPORT3:%.*]], label [[TMP87:%.*]], !prof [[PROF0]]
; CHECK: asan.report3:
; CHECK-NEXT: br i1 [[TMP82]], label [[TMP85:%.*]], label [[TMP86:%.*]]
-; CHECK: 85:
+; CHECK: 93:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP73]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP86]]
-; CHECK: 86:
+; CHECK: 94:
; CHECK-NEXT: br label [[TMP87]]
-; CHECK: 87:
+; CHECK: 95:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP39]], align 4
; CHECK-NEXT: [[TMP88:%.*]] = ptrtoint ptr addrspace(3) [[TMP41]] to i64
; CHECK-NEXT: [[TMP89:%.*]] = lshr i64 [[TMP88]], 3
@@ -154,13 +164,13 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: br i1 [[TMP99]], label [[ASAN_REPORT4:%.*]], label [[TMP102:%.*]], !prof [[PROF0]]
; CHECK: asan.report4:
; CHECK-NEXT: br i1 [[TMP97]], label [[TMP100:%.*]], label [[TMP101:%.*]]
-; CHECK: 100:
+; CHECK: 108:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP88]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP101]]
-; CHECK: 101:
+; CHECK: 109:
; CHECK-NEXT: br label [[TMP102]]
-; CHECK: 102:
+; CHECK: 110:
; CHECK-NEXT: store i8 8, ptr addrspace(3) [[TMP41]], align 8
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll
index bdf86bb53781f05..5e45c5b64f85b16 100755
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan-instr-static-lds-test.ll
@@ -23,9 +23,36 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(1) @malloc(i64 [[TMP8]])
; CHECK-NEXT: store ptr addrspace(1) [[TMP9]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
+; CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 8
+; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP9]], i64 [[TMP64]]
+; CHECK-NEXT: [[TMP66:%.*]] = ptrtoint ptr addrspace(1) [[TMP65]] to i64
+; CHECK-NEXT: [[TMP67:%.*]] = lshr i64 ptrtoint (ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3) to i64), 3
+; CHECK-NEXT: [[TMP68:%.*]] = add i64 [[TMP67]], 2147450880
+; CHECK-NEXT: [[TMP69:%.*]] = inttoptr i64 [[TMP68]] to ptr
+; CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[TMP69]], align 1
+; CHECK-NEXT: [[TMP71:%.*]] = icmp ne i8 [[TMP70]], 0
+; CHECK-NEXT: [[TMP72:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP71]])
+; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[TMP72]], 0
+; CHECK-NEXT: br i1 [[TMP73]], label [[ASAN_REPORT:%.*]], label [[TMP74:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP71]], label [[TMP75:%.*]], label [[TMP76:%.*]]
+; CHECK: 20:
+; CHECK-NEXT: call void @__asan_report_load8(i64 ptrtoint (ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3) to i64)) #[[ATTR6:[0-9]+]]
+; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
+; CHECK-NEXT: br label [[TMP76]]
+; CHECK: 21:
+; CHECK-NEXT: br label [[TMP74]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP77:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP66]], i64 [[TMP77]])
+; CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 8
+; CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP9]], i64 [[TMP78]]
+; CHECK-NEXT: [[TMP80:%.*]] = ptrtoint ptr addrspace(1) [[TMP79]] to i64
+; CHECK-NEXT: [[TMP81:%.*]] = load i64, ptr addrspace(1) getelementptr inbounds ([[TMP0]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 3), align 8
+; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP80]], i64 [[TMP81]])
; CHECK-NEXT: br label [[TMP10]]
-; CHECK: 10:
-; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]
+; CHECK: 28:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[TMP74]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP11]]
@@ -43,16 +70,16 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF0:![0-9]+]]
-; CHECK: asan.report:
+; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT1:%.*]], label [[TMP29:%.*]], !prof [[PROF0]]
+; CHECK: asan.report1:
; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP15]]) #[[ATTR6:[0-9]+]]
+; CHECK: 45:
+; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP15]]) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
+; CHECK: 46:
; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK: 47:
; CHECK-NEXT: store i8 7, ptr addrspace(3) [[TMP12]], align 4
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP14]] to i64
; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 3
@@ -69,16 +96,16 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP38]], [[TMP41]]
; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP42]])
; CHECK-NEXT: [[TMP44:%.*]] = icmp ne i64 [[TMP43]], 0
-; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT1:%.*]], label [[TMP47:%.*]], !prof [[PROF0]]
-; CHECK: asan.report1:
+; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT2:%.*]], label [[TMP47:%.*]], !prof [[PROF0]]
+; CHECK: asan.report2:
; CHECK-NEXT: br i1 [[TMP42]], label [[TMP45:%.*]], label [[TMP46:%.*]]
-; CHECK: 45:
+; CHECK: 63:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP33]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 46:
+; CHECK: 64:
; CHECK-NEXT: br label [[TMP47]]
-; CHECK: 47:
+; CHECK: 65:
; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i64
; CHECK-NEXT: [[TMP49:%.*]] = lshr i64 [[TMP48]], 3
; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[TMP49]], 2147450880
@@ -91,16 +118,16 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP57:%.*]] = and i1 [[TMP53]], [[TMP56]]
; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP57]])
; CHECK-NEXT: [[TMP59:%.*]] = icmp ne i64 [[TMP58]], 0
-; CHECK-NEXT: br i1 [[TMP59]], label [[ASAN_REPORT2:%.*]], label [[TMP62:%.*]], !prof [[PROF0]]
-; CHECK: asan.report2:
+; CHECK-NEXT: br i1 [[TMP59]], label [[ASAN_REPORT3:%.*]], label [[TMP62:%.*]], !prof [[PROF0]]
+; CHECK: asan.report3:
; CHECK-NEXT: br i1 [[TMP57]], label [[TMP60:%.*]], label [[TMP61:%.*]]
-; CHECK: 60:
+; CHECK: 78:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP48]], i64 4) #[[ATTR6]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
; CHECK-NEXT: br label [[TMP61]]
-; CHECK: 61:
+; CHECK: 79:
; CHECK-NEXT: br label [[TMP62]]
-; CHECK: 62:
+; CHECK: 80:
; CHECK-NEXT: store i32 8, ptr addrspace(3) [[TMP14]], align 2
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
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