[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)
Aiden Grossman via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 02:21:13 PDT 2024
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@@ -200,7 +209,9 @@ static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
if (ROV.Op->isExplicit()) {
auto &AssignedValue = IB.getValueFor(*ROV.Op);
if (AssignedValue.isValid()) {
- assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
+ // TODO don't re-assign register operands which are already "locked"
+ // by Target in corresponding InstructionTemplate
+ // assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
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boomanaiden154 wrote:
The TODO here should be fine, but leaving the assert in as a comment is odd. It should probably be removed with additional information added to the todo if necessary.
https://github.com/llvm/llvm-project/pull/89047
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