[llvm] [X86][APX] Remove KEYLOCKER and SHA promotions from EVEX MAP4. (PR #89173)
Freddy Ye via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 17 23:58:37 PDT 2024
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/89173
>From f1bdd62a92b6173f0fc35898d77c1214fe3feae8 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 18 Apr 2024 14:03:32 +0800
Subject: [PATCH 1/5] [X86][APX] Remove KEYLOCKER promotions from EVEX MAP4.
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 19 +--
llvm/lib/Target/X86/X86InstrKL.td | 18 +--
.../X86/keylocker-intrinsics-fast-isel.ll | 146 ------------------
.../MC/Disassembler/X86/apx/keylocker.txt | 102 ------------
llvm/test/MC/X86/apx/keylocker-att.s | 105 -------------
llvm/test/MC/X86/apx/keylocker-intel.s | 101 ------------
6 files changed, 9 insertions(+), 482 deletions(-)
delete mode 100644 llvm/test/MC/Disassembler/X86/apx/keylocker.txt
delete mode 100644 llvm/test/MC/X86/apx/keylocker-att.s
delete mode 100644 llvm/test/MC/X86/apx/keylocker-intel.s
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 4e4241efd63d6b..65e0c06a806e07 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5046,18 +5046,14 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode;
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
- case Intrinsic::x86_encodekey128:
- Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128);
- break;
- case Intrinsic::x86_encodekey256:
- Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256);
- break;
+ case Intrinsic::x86_encodekey128: Opcode = X86::ENCODEKEY128; break;
+ case Intrinsic::x86_encodekey256: Opcode = X86::ENCODEKEY256; break;
}
SDValue Chain = Node->getOperand(0);
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM0, Node->getOperand(3),
SDValue());
- if (Opcode == X86::ENCODEKEY256 || Opcode == X86::ENCODEKEY256_EVEX)
+ if (Opcode == X86::ENCODEKEY256)
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM1, Node->getOperand(4),
Chain.getValue(1));
@@ -6476,18 +6472,17 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
default:
llvm_unreachable("Unexpected opcode!");
case X86ISD::AESENCWIDE128KL:
- Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE128KL);
+ Opcode = X86::AESENCWIDE128KL;
break;
case X86ISD::AESDECWIDE128KL:
- Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE128KL);
+ Opcode = X86::AESDECWIDE128KL;
break;
case X86ISD::AESENCWIDE256KL:
- Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE256KL);
+ Opcode = X86::AESENCWIDE256KL;
break;
case X86ISD::AESDECWIDE256KL:
- Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE256KL);
+ Opcode = X86::AESDECWIDE256KL;
break;
-#undef GET_EGPR_IF_ENABLED
}
SDValue Chain = Node->getOperand(0);
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index 32423e08ed4c53..d5a4be45cc9b10 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -48,7 +48,7 @@ let SchedRW = [WriteSystem] in {
[(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS;
}
- let Predicates = [HasKL, NoEGPR] in {
+ let Predicates = [HasKL] in {
let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8;
@@ -58,17 +58,6 @@ let SchedRW = [WriteSystem] in {
let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
defm "" : Aesencdec<"">, T8;
}
-
- let Predicates = [HasKL, HasEGPR, In64BitMode] in {
- let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
- def ENCODEKEY128_EVEX : Encodekey<0xDA, "encodekey128">, EVEX, T_MAP4;
-
- let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
- def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
-
- let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
- defm "" : Aesencdec<"_EVEX">, EVEX, T_MAP4;
- }
} // SchedRW
multiclass Aesencdecwide<string suffix> {
@@ -80,9 +69,6 @@ multiclass Aesencdecwide<string suffix> {
let SchedRW = [WriteSystem], Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in {
- let Predicates = [HasWIDEKL, NoEGPR] in
+ let Predicates = [HasWIDEKL] in
defm "" : Aesencdecwide<"">, T8;
-
- let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
- defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
} // SchedRW
diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
index f91c4ad0e8e343..5ae1b06b072ff3 100644
--- a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+kl,+widekl | FileCheck %s
-; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+kl,+widekl,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/X86/keylocker-builtins.c
@@ -10,12 +9,6 @@ define void @test_loadiwkey(i32 %ctl, <2 x i64> %intkey, <2 x i64> %enkey_lo, <2
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: loadiwkey %xmm2, %xmm1
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_loadiwkey:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
-; EGPR-NEXT: loadiwkey %xmm2, %xmm1 # encoding: [0xf3,0x0f,0x38,0xdc,0xca]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
tail call void @llvm.x86.loadiwkey(<2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi, i32 %ctl)
ret void
@@ -32,17 +25,6 @@ define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, ptr nocapture %h)
; CHECK-NEXT: movups %xmm5, 64(%rsi)
; CHECK-NEXT: movups %xmm6, 80(%rsi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_encodekey128_u32:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: encodekey128 %edi, %eax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfa,0xc7]
-; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
-; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
-; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
-; EGPR-NEXT: movups %xmm4, 48(%rsi) # encoding: [0x0f,0x11,0x66,0x30]
-; EGPR-NEXT: movups %xmm5, 64(%rsi) # encoding: [0x0f,0x11,0x6e,0x40]
-; EGPR-NEXT: movups %xmm6, 80(%rsi) # encoding: [0x0f,0x11,0x76,0x50]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 %htype, <2 x i64> %key)
%1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
@@ -78,18 +60,6 @@ define i32 @test_encodekey256_u32(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_
; CHECK-NEXT: movups %xmm5, 80(%rsi)
; CHECK-NEXT: movups %xmm6, 96(%rsi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_encodekey256_u32:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: encodekey256 %edi, %eax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfb,0xc7]
-; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
-; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
-; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
-; EGPR-NEXT: movups %xmm3, 48(%rsi) # encoding: [0x0f,0x11,0x5e,0x30]
-; EGPR-NEXT: movups %xmm4, 64(%rsi) # encoding: [0x0f,0x11,0x66,0x40]
-; EGPR-NEXT: movups %xmm5, 80(%rsi) # encoding: [0x0f,0x11,0x6e,0x50]
-; EGPR-NEXT: movups %xmm6, 96(%rsi) # encoding: [0x0f,0x11,0x76,0x60]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_hi)
%1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
@@ -123,13 +93,6 @@ define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_mm_aesenc256kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xde,0x06]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -145,13 +108,6 @@ define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_mm_aesdec256kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdf,0x06]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -167,13 +123,6 @@ define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_mm_aesenc128kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdc,0x06]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -189,13 +138,6 @@ define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test_mm_aesdec128kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdd,0x06]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -226,28 +168,6 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test__mm_aesencwide128kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
-; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
-; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
-; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
-; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
-; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
-; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
-; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
-; EGPR-NEXT: aesencwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x02]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
-; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
-; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
-; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
-; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
-; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
-; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -314,28 +234,6 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test__mm_aesdecwide128kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
-; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
-; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
-; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
-; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
-; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
-; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
-; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
-; EGPR-NEXT: aesdecwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x0a]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
-; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
-; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
-; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
-; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
-; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
-; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -402,28 +300,6 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test__mm_aesencwide256kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
-; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
-; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
-; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
-; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
-; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
-; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
-; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
-; EGPR-NEXT: aesencwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x12]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
-; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
-; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
-; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
-; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
-; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
-; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -490,28 +366,6 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
-;
-; EGPR-LABEL: test__mm_aesdecwide256kl_u8:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
-; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
-; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
-; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
-; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
-; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
-; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
-; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
-; EGPR-NEXT: aesdecwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x1a]
-; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
-; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
-; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
-; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
-; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
-; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
-; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
-; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
diff --git a/llvm/test/MC/Disassembler/X86/apx/keylocker.txt b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
deleted file mode 100644
index c1ddef9ed4233d..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
+++ /dev/null
@@ -1,102 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-## aesdec128kl
-
-# ATT: aesdec128kl 123(%rax,%rbx,4), %xmm12
-# INTEL: aesdec128kl xmm12, [rax + 4*rbx + 123]
-0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b
-
-# ATT: aesdec128kl 291(%r28,%r29,4), %xmm12
-# INTEL: aesdec128kl xmm12, [r28 + 4*r29 + 291]
-0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## aesdec256kl
-
-# ATT: aesdec256kl 123(%rax,%rbx,4), %xmm12
-# INTEL: aesdec256kl xmm12, [rax + 4*rbx + 123]
-0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b
-
-# ATT: aesdec256kl 291(%r28,%r29,4), %xmm12
-# INTEL: aesdec256kl xmm12, [r28 + 4*r29 + 291]
-0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## aesdecwide128kl
-
-# ATT: aesdecwide128kl 123(%rax,%rbx,4)
-# INTEL: aesdecwide128kl [rax + 4*rbx + 123]
-0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b
-
-# ATT: aesdecwide128kl 291(%r28,%r29,4)
-# INTEL: aesdecwide128kl [r28 + 4*r29 + 291]
-0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00
-
-## aesdecwide256kl
-
-# ATT: aesdecwide256kl 123(%rax,%rbx,4)
-# INTEL: aesdecwide256kl [rax + 4*rbx + 123]
-0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b
-
-# ATT: aesdecwide256kl 291(%r28,%r29,4)
-# INTEL: aesdecwide256kl [r28 + 4*r29 + 291]
-0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00
-
-## aesenc128kl
-
-# ATT: aesenc128kl 123(%rax,%rbx,4), %xmm12
-# INTEL: aesenc128kl xmm12, [rax + 4*rbx + 123]
-0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b
-
-# ATT: aesenc128kl 291(%r28,%r29,4), %xmm12
-# INTEL: aesenc128kl xmm12, [r28 + 4*r29 + 291]
-0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## aesenc256kl
-
-# ATT: aesenc256kl 123(%rax,%rbx,4), %xmm12
-# INTEL: aesenc256kl xmm12, [rax + 4*rbx + 123]
-0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b
-
-# ATT: aesenc256kl 291(%r28,%r29,4), %xmm12
-# INTEL: aesenc256kl xmm12, [r28 + 4*r29 + 291]
-0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## aesencwide128kl
-
-# ATT: aesencwide128kl 123(%rax,%rbx,4)
-# INTEL: aesencwide128kl [rax + 4*rbx + 123]
-0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b
-
-# ATT: aesencwide128kl 291(%r28,%r29,4)
-# INTEL: aesencwide128kl [r28 + 4*r29 + 291]
-0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00
-
-## aesencwide256kl
-
-# ATT: aesencwide256kl 123(%rax,%rbx,4)
-# INTEL: aesencwide256kl [rax + 4*rbx + 123]
-0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b
-
-# ATT: aesencwide256kl 291(%r28,%r29,4)
-# INTEL: aesencwide256kl [r28 + 4*r29 + 291]
-0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00
-
-## encodekey128
-
-# ATT: encodekey128 %ecx, %edx
-# INTEL: encodekey128 edx, ecx
-0x62,0xf4,0x7e,0x08,0xda,0xd1
-
-# ATT: encodekey128 %r18d, %r22d
-# INTEL: encodekey128 r22d, r18d
-0x62,0xec,0x7e,0x08,0xda,0xf2
-
-## encodekey256
-
-# ATT: encodekey256 %ecx, %edx
-# INTEL: encodekey256 edx, ecx
-0x62,0xf4,0x7e,0x08,0xdb,0xd1
-
-# ATT: encodekey256 %r18d, %r22d
-# INTEL: encodekey256 r22d, r18d
-0x62,0xec,0x7e,0x08,0xdb,0xf2
diff --git a/llvm/test/MC/X86/apx/keylocker-att.s b/llvm/test/MC/X86/apx/keylocker-att.s
deleted file mode 100644
index 7c8db319df74a7..00000000000000
--- a/llvm/test/MC/X86/apx/keylocker-att.s
+++ /dev/null
@@ -1,105 +0,0 @@
-# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
-# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-
-# ERROR-COUNT-20: error:
-# ERROR-NOT: error:
-
-## aesdec128kl
-
-# CHECK: {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
- {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
-
-# CHECK: aesdec128kl 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesdec128kl 291(%r28,%r29,4), %xmm12
-
-## aesdec256kl
-
-# CHECK: {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
- {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
-
-# CHECK: aesdec256kl 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesdec256kl 291(%r28,%r29,4), %xmm12
-
-## aesdecwide128kl
-
-# CHECK: {evex} aesdecwide128kl 123(%rax,%rbx,4)
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
- {evex} aesdecwide128kl 123(%rax,%rbx,4)
-
-# CHECK: aesdecwide128kl 291(%r28,%r29,4)
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
- aesdecwide128kl 291(%r28,%r29,4)
-
-## aesdecwide256kl
-
-# CHECK: {evex} aesdecwide256kl 123(%rax,%rbx,4)
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
- {evex} aesdecwide256kl 123(%rax,%rbx,4)
-
-# CHECK: aesdecwide256kl 291(%r28,%r29,4)
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
- aesdecwide256kl 291(%r28,%r29,4)
-
-## aesenc128kl
-
-# CHECK: {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
- {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
-
-# CHECK: aesenc128kl 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesenc128kl 291(%r28,%r29,4), %xmm12
-
-## aesenc256kl
-
-# CHECK: {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
- {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
-
-# CHECK: aesenc256kl 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesenc256kl 291(%r28,%r29,4), %xmm12
-
-## aesencwide128kl
-
-# CHECK: {evex} aesencwide128kl 123(%rax,%rbx,4)
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
- {evex} aesencwide128kl 123(%rax,%rbx,4)
-
-# CHECK: aesencwide128kl 291(%r28,%r29,4)
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
- aesencwide128kl 291(%r28,%r29,4)
-
-## aesencwide256kl
-
-# CHECK: {evex} aesencwide256kl 123(%rax,%rbx,4)
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
- {evex} aesencwide256kl 123(%rax,%rbx,4)
-
-# CHECK: aesencwide256kl 291(%r28,%r29,4)
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
- aesencwide256kl 291(%r28,%r29,4)
-
-## encodekey128
-
-# CHECK: {evex} encodekey128 %ecx, %edx
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
- {evex} encodekey128 %ecx, %edx
-
-# CHECK: encodekey128 %r18d, %r22d
-# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
- encodekey128 %r18d, %r22d
-
-## encodekey256
-
-# CHECK: {evex} encodekey256 %ecx, %edx
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
- {evex} encodekey256 %ecx, %edx
-
-# CHECK: encodekey256 %r18d, %r22d
-# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xdb,0xf2]
- encodekey256 %r18d, %r22d
diff --git a/llvm/test/MC/X86/apx/keylocker-intel.s b/llvm/test/MC/X86/apx/keylocker-intel.s
deleted file mode 100644
index b59fa001483d68..00000000000000
--- a/llvm/test/MC/X86/apx/keylocker-intel.s
+++ /dev/null
@@ -1,101 +0,0 @@
-# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
-
-## aesdec128kl
-
-# CHECK: {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
- {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
-
-# CHECK: aesdec128kl xmm12, [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesdec128kl xmm12, [r28 + 4*r29 + 291]
-
-## aesdec256kl
-
-# CHECK: {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
- {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
-
-# CHECK: aesdec256kl xmm12, [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesdec256kl xmm12, [r28 + 4*r29 + 291]
-
-## aesdecwide128kl
-
-# CHECK: {evex} aesdecwide128kl [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
- {evex} aesdecwide128kl [rax + 4*rbx + 123]
-
-# CHECK: aesdecwide128kl [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
- aesdecwide128kl [r28 + 4*r29 + 291]
-
-## aesdecwide256kl
-
-# CHECK: {evex} aesdecwide256kl [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
- {evex} aesdecwide256kl [rax + 4*rbx + 123]
-
-# CHECK: aesdecwide256kl [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
- aesdecwide256kl [r28 + 4*r29 + 291]
-
-## aesenc128kl
-
-# CHECK: {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
- {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
-
-# CHECK: aesenc128kl xmm12, [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesenc128kl xmm12, [r28 + 4*r29 + 291]
-
-## aesenc256kl
-
-# CHECK: {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
- {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
-
-# CHECK: aesenc256kl xmm12, [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
- aesenc256kl xmm12, [r28 + 4*r29 + 291]
-
-## aesencwide128kl
-
-# CHECK: {evex} aesencwide128kl [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
- {evex} aesencwide128kl [rax + 4*rbx + 123]
-
-# CHECK: aesencwide128kl [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
- aesencwide128kl [r28 + 4*r29 + 291]
-
-## aesencwide256kl
-
-# CHECK: {evex} aesencwide256kl [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
- {evex} aesencwide256kl [rax + 4*rbx + 123]
-
-# CHECK: aesencwide256kl [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
- aesencwide256kl [r28 + 4*r29 + 291]
-
-## encodekey128
-
-# CHECK: {evex} encodekey128 edx, ecx
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
- {evex} encodekey128 edx, ecx
-
-# CHECK: encodekey128 r22d, r18d
-# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
- encodekey128 r22d, r18d
-
-## encodekey256
-
-# CHECK: {evex} encodekey256 edx, ecx
-# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
- {evex} encodekey256 edx, ecx
-
-# CHECK: encodekey256 r22d, r18d
-# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xdb,0xf2]
- encodekey256 r22d, r18d
>From a11eef462adc0f6daf9a377d2ed36bcaffeb7add Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 18 Apr 2024 14:05:13 +0800
Subject: [PATCH 2/5] Revert "[X86][MC] Support Enc/Dec for EGPR for promoted
SHA instruction (#75582)"
This reverts commit 037c220702802ea8f26c359c30b69a1c8d33ef0d.
---
llvm/lib/Target/X86/X86InstrAsmAlias.td | 8 --
llvm/lib/Target/X86/X86InstrSSE.td | 94 ++++++--------------
llvm/test/MC/X86/x86_64-asm-match.s | 2 +-
llvm/test/TableGen/x86-fold-tables.inc | 7 --
llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 6 +-
5 files changed, 32 insertions(+), 85 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrAsmAlias.td b/llvm/lib/Target/X86/X86InstrAsmAlias.td
index d06a0c79b46bbb..25b8297502f60d 100644
--- a/llvm/lib/Target/X86/X86InstrAsmAlias.td
+++ b/llvm/lib/Target/X86/X86InstrAsmAlias.td
@@ -894,11 +894,3 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
-// Aliases with explicit %xmm0
-def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
- (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
-def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
- (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
-
-def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
- (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 2b391b60f2c9bb..8542e5ce233364 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6689,31 +6689,31 @@ let Predicates = [HasCRC32, HasEGPR, In64BitMode], OpMap = T_MAP4, OpEnc = EncEV
// FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
- X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
- def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !if(UsesXMM0,
- !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
- [!if(UsesXMM0,
- (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
- (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
- T8, Sched<[sched]>;
-
- def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !if(UsesXMM0,
- !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
- [!if(UsesXMM0,
- (set VR128:$dst, (IntId VR128:$src1,
- (memop addr:$src2), XMM0)),
- (set VR128:$dst, (IntId VR128:$src1,
- (memop addr:$src2))))]>, T8,
- Sched<[sched.Folded, sched.ReadAfterFold]>;
+ X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
+ def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2),
+ !if(UsesXMM0,
+ !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
+ [!if(UsesXMM0,
+ (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
+ (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
+ T8, Sched<[sched]>;
+
+ def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2),
+ !if(UsesXMM0,
+ !strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
+ [!if(UsesXMM0,
+ (set VR128:$dst, (IntId VR128:$src1,
+ (memop addr:$src2), XMM0)),
+ (set VR128:$dst, (IntId VR128:$src1,
+ (memop addr:$src2))))]>, T8,
+ Sched<[sched.Folded, sched.ReadAfterFold]>;
}
-let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
+let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -6740,7 +6740,7 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
let Uses=[XMM0] in
defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
- SchedWriteVecIMul.XMM, "", 1>;
+ SchedWriteVecIMul.XMM, 1>;
defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
SchedWriteVecIMul.XMM>;
@@ -6748,47 +6748,11 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
SchedWriteVecIMul.XMM>;
}
-let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in {
- def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, u8imm:$src3),
- "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- [(set VR128:$dst,
- (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
- (i8 timm:$src3)))]>,
- EVEX, NoCD8, T_MAP4, Sched<[SchedWriteVecIMul.XMM]>;
- def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
- "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- [(set VR128:$dst,
- (int_x86_sha1rnds4 VR128:$src1,
- (memop addr:$src2),
- (i8 timm:$src3)))]>,
- EVEX, NoCD8, T_MAP4,
- Sched<[SchedWriteVecIMul.XMM.Folded,
- SchedWriteVecIMul.XMM.ReadAfterFold]>;
-
- defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
- SchedWriteVecIMul.XMM, "_EVEX">,
- EVEX, NoCD8, T_MAP4;
- defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
- SchedWriteVecIMul.XMM, "_EVEX">,
- EVEX, NoCD8, T_MAP4;
- defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
- SchedWriteVecIMul.XMM, "_EVEX">,
- EVEX, NoCD8, T_MAP4;
-
- let Uses=[XMM0] in
- defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
- SchedWriteVecIMul.XMM, "_EVEX", 1>,
- EVEX, NoCD8, T_MAP4;
-
- defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
- SchedWriteVecIMul.XMM, "_EVEX">,
- EVEX, NoCD8, T_MAP4;
- defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
- SchedWriteVecIMul.XMM, "_EVEX">,
- EVEX, NoCD8, T_MAP4;
-}
+// Aliases with explicit %xmm0
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+ (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+ (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
//===----------------------------------------------------------------------===//
// AES-NI Instructions
diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s
index 68d375ec3e4cd5..441842bf188d0f 100644
--- a/llvm/test/MC/X86/x86_64-asm-match.s
+++ b/llvm/test/MC/X86/x86_64-asm-match.s
@@ -11,7 +11,7 @@
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
// CHECK: Opcode result: complete match, selecting this opcode
-// CHECK: AsmMatcher: found 4 encodings with mnemonic 'sha1rnds4'
+// CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
// CHECK: Trying to match opcode SHA1RNDS4rri
// CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 6f983d2efabe9b..c8f382d45bf6e6 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -2247,19 +2247,12 @@ static const X86FoldTableEntry Table2[] = {
{X86::SBB8rr, X86::SBB8rm, 0},
{X86::SBB8rr_ND, X86::SBB8rm_ND, 0},
{X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16},
- {X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, TB_ALIGN_16},
{X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16},
- {X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, TB_ALIGN_16},
{X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16},
- {X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, TB_ALIGN_16},
{X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16},
- {X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, TB_ALIGN_16},
{X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16},
- {X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, TB_ALIGN_16},
{X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16},
- {X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, TB_ALIGN_16},
{X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16},
- {X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, TB_ALIGN_16},
{X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16},
{X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16},
{X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE},
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 5871e678b16ebd..0e3674751fde6a 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -33,10 +33,8 @@ struct ManualMapEntry {
};
// List of instructions requiring explicitly aligned memory.
-const char *ExplicitAlign[] = {
- "MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD",
- "MOVNTDQ", "MOVNTDQA", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE",
- "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"};
+const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",
+ "MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
// List of instructions NOT requiring explicit memory alignment.
const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",
>From abc31d6ab138144ec9cd0e1f27d0dd78ecfd1ec9 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 18 Apr 2024 14:22:53 +0800
Subject: [PATCH 3/5] cont. fix for SHA
---
llvm/test/CodeGen/X86/sha.ll | 83 --------------
llvm/test/MC/Disassembler/X86/apx/sha.txt | 124 ---------------------
llvm/test/MC/X86/apx/sha-att.s | 127 ----------------------
llvm/test/MC/X86/apx/sha-intel.s | 123 ---------------------
4 files changed, 457 deletions(-)
delete mode 100644 llvm/test/MC/Disassembler/X86/apx/sha.txt
delete mode 100644 llvm/test/MC/X86/apx/sha-att.s
delete mode 100644 llvm/test/MC/X86/apx/sha-intel.s
diff --git a/llvm/test/CodeGen/X86/sha.ll b/llvm/test/CodeGen/X86/sha.ll
index 65222ba74023f4..f0bca34511cde1 100644
--- a/llvm/test/CodeGen/X86/sha.ll
+++ b/llvm/test/CodeGen/X86/sha.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: llc < %s -mattr=+sha,+avx2 -mtriple=x86_64-unknown-unknown --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
-; RUN: llc < %s -mattr=+sha,+egpr -mtriple=x86_64-unknown-unknown --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=EGPR
declare <4 x i32> @llvm.x86.sha1rnds4(<4 x i32>, <4 x i32>, i8) nounwind readnone
@@ -15,11 +14,6 @@ define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1rnds4 $3, %xmm1, %xmm0 # encoding: [0x0f,0x3a,0xcc,0xc1,0x03]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1rnds4rr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1rnds4 $3, %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x3a,0xcc,0xc1,0x03]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)
ret <4 x i32> %0
@@ -35,11 +29,6 @@ define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, ptr %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # encoding: [0x0f,0x3a,0xcc,0x07,0x03]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1rnds4rm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x3a,0xcc,0x07,0x03]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
@@ -58,11 +47,6 @@ define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1nexte %xmm1, %xmm0 # encoding: [0x0f,0x38,0xc8,0xc1]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1nexterr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1nexte %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc8,0xc1]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
@@ -78,11 +62,6 @@ define <4 x i32> @test_sha1nexterm(<4 x i32> %a, ptr %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1nexte (%rdi), %xmm0 # encoding: [0x0f,0x38,0xc8,0x07]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1nexterm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1nexte (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc8,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
@@ -101,11 +80,6 @@ define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1msg1 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xc9,0xc1]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1msg1rr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1msg1 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc9,0xc1]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
@@ -121,11 +95,6 @@ define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, ptr %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1msg1 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xc9,0x07]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1msg1rm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1msg1 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xc9,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
@@ -144,11 +113,6 @@ define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1msg2 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xca,0xc1]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1msg2rr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1msg2 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xca,0xc1]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
@@ -164,11 +128,6 @@ define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, ptr %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha1msg2 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xca,0x07]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1msg2rm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1msg2 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xca,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
@@ -193,14 +152,6 @@ define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) n
; AVX-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 # encoding: [0x0f,0x38,0xcb,0xd9]
; AVX-NEXT: vmovaps %xmm3, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc3]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha256rnds2rr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movaps %xmm0, %xmm3 # encoding: [0x0f,0x28,0xd8]
-; EGPR-NEXT: movaps %xmm2, %xmm0 # encoding: [0x0f,0x28,0xc2]
-; EGPR-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcb,0xd9]
-; EGPR-NEXT: movaps %xmm3, %xmm0 # encoding: [0x0f,0x28,0xc3]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
ret <4 x i32> %0
@@ -222,14 +173,6 @@ define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, ptr %b, <4 x i32> %c) nounwin
; AVX-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2 # encoding: [0x0f,0x38,0xcb,0x17]
; AVX-NEXT: vmovaps %xmm2, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc2]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha256rnds2rm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: movaps %xmm0, %xmm2 # encoding: [0x0f,0x28,0xd0]
-; EGPR-NEXT: movaps %xmm1, %xmm0 # encoding: [0x0f,0x28,0xc1]
-; EGPR-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm2 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcb,0x17]
-; EGPR-NEXT: movaps %xmm2, %xmm0 # encoding: [0x0f,0x28,0xc2]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
@@ -248,11 +191,6 @@ define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha256msg1 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xcc,0xc1]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha256msg1rr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha256msg1 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcc,0xc1]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
@@ -268,11 +206,6 @@ define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, ptr %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha256msg1 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xcc,0x07]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha256msg1rm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha256msg1 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcc,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
@@ -291,11 +224,6 @@ define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha256msg2 %xmm1, %xmm0 # encoding: [0x0f,0x38,0xcd,0xc1]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha256msg2rr:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha256msg2 %xmm1, %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcd,0xc1]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
@@ -311,11 +239,6 @@ define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, ptr %b) nounwind uwtable {
; AVX: # %bb.0: # %entry
; AVX-NEXT: sha256msg2 (%rdi), %xmm0 # encoding: [0x0f,0x38,0xcd,0x07]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha256msg2rm:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha256msg2 (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xcd,0x07]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
@@ -335,12 +258,6 @@ define <8 x i32> @test_sha1rnds4_zero_extend(<4 x i32> %a, ptr %b) nounwind uwta
; AVX-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # encoding: [0x0f,0x3a,0xcc,0x07,0x03]
; AVX-NEXT: vmovaps %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x28,0xc0]
; AVX-NEXT: retq # encoding: [0xc3]
-;
-; EGPR-LABEL: test_sha1rnds4_zero_extend:
-; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: sha1rnds4 $3, (%rdi), %xmm0 # EVEX TO LEGACY Compression encoding: [0x0f,0x3a,0xcc,0x07,0x03]
-; EGPR-NEXT: xorps %xmm1, %xmm1 # encoding: [0x0f,0x57,0xc9]
-; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <4 x i32>, ptr %b
%1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha.txt b/llvm/test/MC/Disassembler/X86/apx/sha.txt
deleted file mode 100644
index 6385ba754aba4e..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/sha.txt
+++ /dev/null
@@ -1,124 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-## sha1msg1
-
-# ATT: sha1msg1 %xmm13, %xmm12
-# INTEL: sha1msg1 xmm12, xmm13
-0x62,0x54,0x7c,0x08,0xd9,0xe5
-
-# ATT: sha1msg1 123(%rax,%rbx,4), %xmm12
-# INTEL: sha1msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
-0x62,0x74,0x7c,0x08,0xd9,0x64,0x98,0x7b
-
-# ATT: sha1msg1 %xmm13, %xmm12
-# INTEL: sha1msg1 xmm12, xmm13
-0x45,0x0f,0x38,0xc9,0xe5
-
-# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
-# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## sha1msg2
-
-# ATT: sha1msg2 %xmm13, %xmm12
-# INTEL: sha1msg2 xmm12, xmm13
-0x62,0x54,0x7c,0x08,0xda,0xe5
-
-# ATT: sha1msg2 123(%rax,%rbx,4), %xmm12
-# INTEL: sha1msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
-0x62,0x74,0x7c,0x08,0xda,0x64,0x98,0x7b
-
-# ATT: sha1msg2 %xmm13, %xmm12
-# INTEL: sha1msg2 xmm12, xmm13
-0x45,0x0f,0x38,0xca,0xe5
-
-# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
-# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## sha1nexte
-
-# ATT: sha1nexte %xmm13, %xmm12
-# INTEL: sha1nexte xmm12, xmm13
-0x62,0x54,0x7c,0x08,0xd8,0xe5
-
-# ATT: sha1nexte 123(%rax,%rbx,4), %xmm12
-# INTEL: sha1nexte xmm12, xmmword ptr [rax + 4*rbx + 123]
-0x62,0x74,0x7c,0x08,0xd8,0x64,0x98,0x7b
-
-# ATT: sha1nexte %xmm13, %xmm12
-# INTEL: sha1nexte xmm12, xmm13
-0x45,0x0f,0x38,0xc8,0xe5
-
-# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
-# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## sha1rnds4
-
-# ATT: sha1rnds4 $123, %xmm13, %xmm12
-# INTEL: sha1rnds4 xmm12, xmm13, 123
-0x62,0x54,0x7c,0x08,0xd4,0xe5,0x7b
-
-# ATT: sha1rnds4 $123, 123(%rax,%rbx,4), %xmm12
-# INTEL: sha1rnds4 xmm12, xmmword ptr [rax + 4*rbx + 123], 123
-0x62,0x74,0x7c,0x08,0xd4,0x64,0x98,0x7b,0x7b
-
-# ATT: sha1rnds4 $123, %xmm13, %xmm12
-# INTEL: sha1rnds4 xmm12, xmm13, 123
-0x45,0x0f,0x3a,0xcc,0xe5,0x7b
-
-# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
-# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
-0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b
-
-## sha256msg1
-
-# ATT: sha256msg1 %xmm13, %xmm12
-# INTEL: sha256msg1 xmm12, xmm13
-0x62,0x54,0x7c,0x08,0xdc,0xe5
-
-# ATT: sha256msg1 123(%rax,%rbx,4), %xmm12
-# INTEL: sha256msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
-0x62,0x74,0x7c,0x08,0xdc,0x64,0x98,0x7b
-
-# ATT: sha256msg1 %xmm13, %xmm12
-# INTEL: sha256msg1 xmm12, xmm13
-0x45,0x0f,0x38,0xcc,0xe5
-
-# ATT: sha256msg1 291(%r28,%r29,4), %xmm12
-# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## sha256msg2
-
-# ATT: sha256msg2 %xmm13, %xmm12
-# INTEL: sha256msg2 xmm12, xmm13
-0x62,0x54,0x7c,0x08,0xdd,0xe5
-
-# ATT: sha256msg2 123(%rax,%rbx,4), %xmm12
-# INTEL: sha256msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
-0x62,0x74,0x7c,0x08,0xdd,0x64,0x98,0x7b
-
-# ATT: sha256msg2 %xmm13, %xmm12
-# INTEL: sha256msg2 xmm12, xmm13
-0x45,0x0f,0x38,0xcd,0xe5
-
-# ATT: sha256msg2 291(%r28,%r29,4), %xmm12
-# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
-
-## sha256rnds2
-
-# ATT: sha256rnds2 %xmm0, 123(%rax,%rbx,4), %xmm12
-# INTEL: sha256rnds2 xmm12, xmmword ptr [rax + 4*rbx + 123], xmm0
-0x62,0x74,0x7c,0x08,0xdb,0x64,0x98,0x7b
-
-# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12
-# INTEL: sha256rnds2 xmm12, xmm13, xmm0
-0x45,0x0f,0x38,0xcb,0xe5
-
-# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
-# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
-0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/sha-att.s b/llvm/test/MC/X86/apx/sha-att.s
deleted file mode 100644
index 3b60ad8e6c0de5..00000000000000
--- a/llvm/test/MC/X86/apx/sha-att.s
+++ /dev/null
@@ -1,127 +0,0 @@
-# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
-# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-
-# ERROR-COUNT-27: error:
-# ERROR-NOT: error:
-
-## sha1msg1
-
-# CHECK: {evex} sha1msg1 %xmm13, %xmm12
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xd9,0xe5]
- {evex} sha1msg1 %xmm13, %xmm12
-
-# CHECK: {evex} sha1msg1 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xd9,0x64,0x98,0x7b]
- {evex} sha1msg1 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha1msg1 %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
- sha1msg1 %xmm13, %xmm12
-
-# CHECK: sha1msg1 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha1msg1 291(%r28,%r29,4), %xmm12
-
-## sha1msg2
-
-# CHECK: {evex} sha1msg2 %xmm13, %xmm12
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xda,0xe5]
- {evex} sha1msg2 %xmm13, %xmm12
-
-# CHECK: {evex} sha1msg2 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xda,0x64,0x98,0x7b]
- {evex} sha1msg2 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha1msg2 %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
- sha1msg2 %xmm13, %xmm12
-
-# CHECK: sha1msg2 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha1msg2 291(%r28,%r29,4), %xmm12
-
-## sha1nexte
-
-# CHECK: {evex} sha1nexte %xmm13, %xmm12
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xd8,0xe5]
- {evex} sha1nexte %xmm13, %xmm12
-
-# CHECK: {evex} sha1nexte 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xd8,0x64,0x98,0x7b]
- {evex} sha1nexte 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha1nexte %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
- sha1nexte %xmm13, %xmm12
-
-# CHECK: sha1nexte 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha1nexte 291(%r28,%r29,4), %xmm12
-
-## sha1rnds4
-
-# CHECK: {evex} sha1rnds4 $123, %xmm13, %xmm12
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xd4,0xe5,0x7b]
- {evex} sha1rnds4 $123, %xmm13, %xmm12
-
-# CHECK: {evex} sha1rnds4 $123, 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xd4,0x64,0x98,0x7b,0x7b]
- {evex} sha1rnds4 $123, 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha1rnds4 $123, %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
- sha1rnds4 $123, %xmm13, %xmm12
-
-# CHECK: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
- sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
-
-## sha256msg1
-
-# CHECK: {evex} sha256msg1 %xmm13, %xmm12
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xdc,0xe5]
- {evex} sha256msg1 %xmm13, %xmm12
-
-# CHECK: {evex} sha256msg1 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xdc,0x64,0x98,0x7b]
- {evex} sha256msg1 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha256msg1 %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
- sha256msg1 %xmm13, %xmm12
-
-# CHECK: sha256msg1 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha256msg1 291(%r28,%r29,4), %xmm12
-
-## sha256msg2
-
-# CHECK: {evex} sha256msg2 %xmm13, %xmm12
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xdd,0xe5]
- {evex} sha256msg2 %xmm13, %xmm12
-
-# CHECK: {evex} sha256msg2 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xdd,0x64,0x98,0x7b]
- {evex} sha256msg2 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha256msg2 %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
- sha256msg2 %xmm13, %xmm12
-
-# CHECK: sha256msg2 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha256msg2 291(%r28,%r29,4), %xmm12
-
-## sha256rnds2
-
-# CHECK: {evex} sha256rnds2 %xmm0, 123(%rax,%rbx,4), %xmm12
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xdb,0x64,0x98,0x7b]
- {evex} sha256rnds2 %xmm0, 123(%rax,%rbx,4), %xmm12
-
-# CHECK: sha256rnds2 %xmm0, %xmm13, %xmm12
-# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
- sha256rnds2 %xmm0, %xmm13, %xmm12
-
-# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
diff --git a/llvm/test/MC/X86/apx/sha-intel.s b/llvm/test/MC/X86/apx/sha-intel.s
deleted file mode 100644
index ceb76195adeeb3..00000000000000
--- a/llvm/test/MC/X86/apx/sha-intel.s
+++ /dev/null
@@ -1,123 +0,0 @@
-# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
-
-## sha1msg1
-
-# CHECK: {evex} sha1msg1 xmm12, xmm13
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xd9,0xe5]
- {evex} sha1msg1 xmm12, xmm13
-
-# CHECK: {evex} sha1msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xd9,0x64,0x98,0x7b]
- {evex} sha1msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
-
-# CHECK: sha1msg1 xmm12, xmm13
-# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
- sha1msg1 xmm12, xmm13
-
-# CHECK: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-
-## sha1msg2
-
-# CHECK: {evex} sha1msg2 xmm12, xmm13
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xda,0xe5]
- {evex} sha1msg2 xmm12, xmm13
-
-# CHECK: {evex} sha1msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xda,0x64,0x98,0x7b]
- {evex} sha1msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
-
-# CHECK: sha1msg2 xmm12, xmm13
-# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
- sha1msg2 xmm12, xmm13
-
-# CHECK: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-
-## sha1nexte
-
-# CHECK: {evex} sha1nexte xmm12, xmm13
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xd8,0xe5]
- {evex} sha1nexte xmm12, xmm13
-
-# CHECK: {evex} sha1nexte xmm12, xmmword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xd8,0x64,0x98,0x7b]
- {evex} sha1nexte xmm12, xmmword ptr [rax + 4*rbx + 123]
-
-# CHECK: sha1nexte xmm12, xmm13
-# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
- sha1nexte xmm12, xmm13
-
-# CHECK: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
-
-## sha1rnds4
-
-# CHECK: {evex} sha1rnds4 xmm12, xmm13, 123
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xd4,0xe5,0x7b]
- {evex} sha1rnds4 xmm12, xmm13, 123
-
-# CHECK: {evex} sha1rnds4 xmm12, xmmword ptr [rax + 4*rbx + 123], 123
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xd4,0x64,0x98,0x7b,0x7b]
- {evex} sha1rnds4 xmm12, xmmword ptr [rax + 4*rbx + 123], 123
-
-# CHECK: sha1rnds4 xmm12, xmm13, 123
-# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
- sha1rnds4 xmm12, xmm13, 123
-
-# CHECK: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
- sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
-
-## sha256msg1
-
-# CHECK: {evex} sha256msg1 xmm12, xmm13
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xdc,0xe5]
- {evex} sha256msg1 xmm12, xmm13
-
-# CHECK: {evex} sha256msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xdc,0x64,0x98,0x7b]
- {evex} sha256msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
-
-# CHECK: sha256msg1 xmm12, xmm13
-# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
- sha256msg1 xmm12, xmm13
-
-# CHECK: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-
-## sha256msg2
-
-# CHECK: {evex} sha256msg2 xmm12, xmm13
-# CHECK: encoding: [0x62,0x54,0x7c,0x08,0xdd,0xe5]
- {evex} sha256msg2 xmm12, xmm13
-
-# CHECK: {evex} sha256msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xdd,0x64,0x98,0x7b]
- {evex} sha256msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
-
-# CHECK: sha256msg2 xmm12, xmm13
-# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
- sha256msg2 xmm12, xmm13
-
-# CHECK: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-
-## sha256rnds2
-
-# CHECK: {evex} sha256rnds2 xmm12, xmmword ptr [rax + 4*rbx + 123], xmm0
-# CHECK: encoding: [0x62,0x74,0x7c,0x08,0xdb,0x64,0x98,0x7b]
- {evex} sha256rnds2 xmm12, xmmword ptr [rax + 4*rbx + 123], xmm0
-
-# CHECK: sha256rnds2 xmm12, xmm13, xmm0
-# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
- sha256rnds2 xmm12, xmm13, xmm0
-
-# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
-# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
- sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
>From d49676df7fb7b59de31b4be765386d19a5472153 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 18 Apr 2024 14:42:49 +0800
Subject: [PATCH 4/5] clang-format
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 65e0c06a806e07..76043f8d070794 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5046,8 +5046,12 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode;
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
- case Intrinsic::x86_encodekey128: Opcode = X86::ENCODEKEY128; break;
- case Intrinsic::x86_encodekey256: Opcode = X86::ENCODEKEY256; break;
+ case Intrinsic::x86_encodekey128:
+ Opcode = X86::ENCODEKEY128;
+ break;
+ case Intrinsic::x86_encodekey256:
+ Opcode = X86::ENCODEKEY256;
+ break;
}
SDValue Chain = Node->getOperand(0);
>From ec540b6f4cea6a9df180d4dcd5b54da1ec4b149f Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 18 Apr 2024 14:52:06 +0800
Subject: [PATCH 5/5] address comments.
---
llvm/lib/Target/X86/X86InstrAsmAlias.td | 5 +++++
llvm/lib/Target/X86/X86InstrSSE.td | 5 -----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrAsmAlias.td b/llvm/lib/Target/X86/X86InstrAsmAlias.td
index 25b8297502f60d..f67c03f98e876c 100644
--- a/llvm/lib/Target/X86/X86InstrAsmAlias.td
+++ b/llvm/lib/Target/X86/X86InstrAsmAlias.td
@@ -894,3 +894,8 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
+// Aliases with explicit %xmm0
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+ (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
+def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
+ (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 8542e5ce233364..855bd6dcab526b 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6748,11 +6748,6 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
SchedWriteVecIMul.XMM>;
}
-// Aliases with explicit %xmm0
-def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
- (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
-def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
- (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
//===----------------------------------------------------------------------===//
// AES-NI Instructions
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