[llvm] 43eb5e2 - [RISCV] Remove unused Predicates for I and E extensions. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-04-17T23:24:31-07:00
New Revision: 43eb5e2d4054104dcdd9fadeea8da8bacab6d338

URL: https://github.com/llvm/llvm-project/commit/43eb5e2d4054104dcdd9fadeea8da8bacab6d338
DIFF: https://github.com/llvm/llvm-project/commit/43eb5e2d4054104dcdd9fadeea8da8bacab6d338.diff

LOG: [RISCV] Remove unused Predicates for I and E extensions. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFeatures.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f830ead5dd692a..8c434a23b10ee7 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -15,9 +15,7 @@
 def FeatureStdExtI
     : SubtargetFeature<"i", "HasStdExtI", "true",
                        "'I' (Base Integer Instruction Set)">;
-def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">,
-                 AssemblerPredicate<(all_of FeatureStdExtI),
-                                    "'I' (Base Integer Instruction Set)">;
+
 def FeatureStdExtZic64b
     : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
                        "'Zic64b' (Cache Block Size Is 64 Bytes)">;
@@ -1170,8 +1168,6 @@ def RV64           : HwMode<"+64bit", [IsRV64]>;
 def FeatureRVE
     : SubtargetFeature<"e", "IsRVE", "true",
                        "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
-def IsRVE : Predicate<"Subtarget->isRVE()">,
-            AssemblerPredicate<(all_of FeatureRVE)>;
 
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",