[llvm] [llvm][mc][riscv] MC support of T-Head vector extension (xtheadvector) (PR #84447)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 17 22:00:27 PDT 2024
================
@@ -0,0 +1,990 @@
+//===-- RISCVInstrInfoXTHeadV.td ---------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the standard 'V' Vector
+/// extension, version 0.7.1.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def XTHeadVTypeIAsmOperand : AsmOperandClass {
+ let Name = "XTHeadVTypeI";
+ let ParserMethod = "parseXTHeadVTypeI";
+ let DiagnosticType = "InvalidXTHeadVTypeI";
+ let RenderMethod = "addVTypeIOperands";
+}
+
+def XTHeadVTypeI : Operand<XLenVT> {
+ let ParserMatchClass = XTHeadVTypeIAsmOperand;
+ let PrintMethod = "printXTHeadVTypeI";
+ let DecoderMethod = "decodeUImmOperand<11>";
+ let OperandType = "OPERAND_XTHEADVTYPEI";
+ let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isUInt<11>(Imm);
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+class TH_VLoadStore<bits<3> nf, RISCVOpcode opcode,
+ bits<3> mop, bits<3> width, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> rd;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop;
+ let Inst{25} = vm;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0, RVVConstraint = VMConstraint in {
+ class TH_VLxU<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b00000;
+ }
+ class TH_VLx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b00000;
+ }
+ class TH_VLxUFF<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b000, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b10000;
+ }
+ class TH_VLxFF<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b100, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b10000;
+ }
+ class TH_VLSxU<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b010, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLSx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b110, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLXxU<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b011, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VLXx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_LOAD_FP, 0b111, width, (outs VR:$rd),
+ (ins GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ class TH_VSx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b000, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VMaskOp:$vm),
+ opcodestr, "$rd, ${rs1}$vm"> {
+ let rs2 = 0b00000;
+ }
+ class TH_VSSx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b010, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VSXx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b011, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+ class TH_VSUXx<bits<3> nf, bits<3> width, string opcodestr>
+ : TH_VLoadStore<nf, OPC_STORE_FP, 0b111, width, (outs),
+ (ins VR:$rd, GPRMemZeroOffset:$rs1, VR:$rs2, VMaskOp:$vm),
+ opcodestr, "$rd, $rs1, $rs2$vm">;
+}
+
+multiclass TH_VWSMAC_V_X<string opcodestr, bits<6> funct6> {
+ def V : VALUrVV<funct6, OPIVV, opcodestr # ".vv">,
+ Sched<[WriteVIWMulAddV_WorstCase, ReadVIWMulAddV_WorstCase,
+ ReadVIWMulAddV_WorstCase, ReadVMask]>;
+ def X : VALUrVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase,
+ ReadVIWMulAddX_WorstCase, ReadVMask]>;
+}
+
+multiclass TH_VWSMAC_X<string opcodestr, bits<6> funct6> {
+ def X : VALUrVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase,
+ ReadVIWMulAddX_WorstCase, ReadVMask]>;
+}
+
+multiclass TH_VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
+ def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
+ Sched<[WriteVNClipV_WorstCase, ReadVNClipV_WorstCase,
+ ReadVNClipV_WorstCase, ReadVMask]>;
+ def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVNClipX_WorstCase, ReadVNClipV_WorstCase,
+ ReadVNClipX_WorstCase, ReadVMask]>;
+ def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
+ Sched<[WriteVNClipI_WorstCase, ReadVNClipV_WorstCase,
+ ReadVMask]>;
+}
+
+multiclass TH_VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
+ def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
+ Sched<[WriteVNShiftV_WorstCase, ReadVNShiftV_WorstCase,
+ ReadVNShiftV_WorstCase, ReadVMask]>;
+ def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
+ Sched<[WriteVNShiftX_WorstCase, ReadVNShiftV_WorstCase,
+ ReadVNShiftX_WorstCase, ReadVMask]>;
+ def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
+ Sched<[WriteVNShiftI_WorstCase, ReadVNShiftV_WorstCase,
+ ReadVMask]>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// rvv 0.7.1 set vm=1 for `op vd, vs2, vs1, v0`
+class TH_VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VR:$vd),
+ (ins VR:$vs2, VR:$vs1, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $vs1, v0"> {
+ let vm = 1;
+}
+
+// rvv 0.7.1 set vm=1 for `op vd, vs2, rs1, v0`
+class TH_VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VR:$vd),
+ (ins VR:$vs2, GPR:$rs1, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $rs1, v0"> {
+ let vm = 1;
+}
+
+// rvv 0.7.1 set vm=1 for `op vd, vs2, imm, v0`
+class TH_VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+ : RVInstIVI<funct6, (outs VR:$vd),
+ (ins VR:$vs2, optype:$imm, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $imm, v0"> {
+ let vm = 1;
+}
+
+multiclass TH_VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
+ def VM : TH_VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
+ Sched<[WriteVICALUV_WorstCase, ReadVICALUV_WorstCase,
+ ReadVICALUV_WorstCase, ReadVMask]>;
+ def XM : TH_VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
+ Sched<[WriteVICALUX_WorstCase, ReadVICALUV_WorstCase,
+ ReadVICALUX_WorstCase, ReadVMask]>;
+}
+
+multiclass TH_VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
+ : TH_VALUm_IV_V_X<opcodestr, funct6> {
+ def IM : TH_VALUmVI<funct6, opcodestr # ".vim">,
+ Sched<[WriteVICALUI_WorstCase, ReadVICALUV_WorstCase,
+ ReadVMask]>;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+class TH_InstVAMO<bits<5> amoop, bits<3> width, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> rs1;
+ bit wd;
+ bit vm;
+
+ let Inst{31-27} = amoop;
+ let Inst{26} = wd;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width;
+ let Inst{6-0} = OPC_AMO.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
+// vamo vd, vs2, (rs1), vd, vm
----------------
topperc wrote:
Is this syntax only documented in the 0.8 spec and not the 0.7.1 spec?
https://github.com/llvm/llvm-project/pull/84447
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