[llvm] [RISCV] Defer forming x0, x0 vsetvlis until after insertion (PR #89089)

[Luke Lau via llvm-commits]

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@@ -1603,6 +1521,34 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
   }
 }
 
+void RISCVInsertVSETVLI::convertToX0X0(MachineBasicBlock &MBB) {
+  VSETVLIInfo Info = BlockInfo[MBB.getNumber()].Pred;
+  for (MachineInstr &MI : MBB) {
+    if (isVectorConfigInstr(MI)) {
+      VSETVLIInfo MIInfo = getInfoForVSETVLI(MI, *MRI);
+
+      // If VL doesn't change going from Info to MIInfo, then we can use x0,x0
+      DemandedFields Demanded;
+      Demanded.demandVL();
+      bool HasSameVL = Info.isCompatible(Demanded, MIInfo, *MRI);
+      // An AVL from a phi node where the incoming values are the output vls of
+      // the last vsetvlis in a block doesn't change the VL.
+      HasSameVL |= !needVSETVLIPHI(MIInfo, MBB, Demanded);
+
+      if (HasSameVL && MI.getOperand(0).isDead()) {
+        MI.setDesc(TII->get(RISCV::PseudoVSETVLIX0));
+        MI.getOperand(0).ChangeToRegister(RISCV::X0, /*isDef*/ true);
+        MI.getOperand(0).setIsDead(true);
+        MI.getOperand(1).ChangeToRegister(RISCV::X0, /*isDef*/ false);
+        MI.getOperand(1).setIsKill(true);
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lukel97 wrote:

Need to add an implicit VL operand here

https://github.com/llvm/llvm-project/pull/89089