[llvm] 2c22a0c - [InstCombine] Add test case for turning sub into xor using dominating condition. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-04-17T10:40:25-07:00
New Revision: 2c22a0c16d1cb844eac142156ba67098627a336c

URL: https://github.com/llvm/llvm-project/commit/2c22a0c16d1cb844eac142156ba67098627a336c
DIFF: https://github.com/llvm/llvm-project/commit/2c22a0c16d1cb844eac142156ba67098627a336c.diff

LOG: [InstCombine] Add test case for turning sub into xor using dominating condition. NFC

I plan to disable using dominating conditions for turning sub into
xor, but first we need that demonstrates it currently happens.

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/sub-xor.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/sub-xor.ll b/llvm/test/Transforms/InstCombine/sub-xor.ll
index 71da73d51ae37e..b4e87d0405fc48 100644
--- a/llvm/test/Transforms/InstCombine/sub-xor.ll
+++ b/llvm/test/Transforms/InstCombine/sub-xor.ll
@@ -157,3 +157,26 @@ define <2 x i8> @xor_add_splat_undef(<2 x i8> %x) {
   %add = add <2 x i8> %xor, <i8 42, i8 42>
   ret <2 x i8> %add
 }
+
+define i32 @xor_dominating_cond(i32 %x) {
+; CHECK-LABEL: @xor_dominating_cond(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[X:%.*]], 256
+; CHECK-NEXT:    br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = xor i32 [[X]], 255
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 [[X]]
+;
+entry:
+  %cond = icmp ult i32 %x, 256
+  br i1 %cond, label %if.then, label %if.end
+
+if.then:
+  %a = sub i32 255, %x
+  ret i32 %a
+
+if.end:
+  ret i32 %x
+}