[llvm] [RISCV] Fix CASE_VFMA_CHANGE_OPCODE_VV to handle MF4 pseudos (PR #88947)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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michaelmaitland wrote:

You did try and test this permutation (VSQRT, MF2, E16) and (VFMA MF4, E16)

This is the reduced test that fails in our downstream:
```
; RUN: llc %s -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 | FileCheck %s
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <2 x half> @llvm.sqrt.v2f16(<2 x half>) #0

define <2 x half> @sqrt_v2f16() #1 {
  %1 = tail call ninf contract afn <2 x half> @llvm.sqrt.v2f16(<2 x half> <half 0xH3C00, half 0xH3C00>)
  ret <2 x half> %1
}

attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
```

This generates the MIR I have include in the patch. This reduced LLVM test case does not fail in upstream.

I cannot get a (VFMA MF4, E16) that calls `commuteInstructionImpl` as we would like. I'm open to suggestions on an LLVM test case, but I'm getting to the point where I'm not sure its worth the time to keep looking for one when we have one that works here.

https://github.com/llvm/llvm-project/pull/88947