[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[Craig Topper via llvm-commits]

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@@ -45,6 +45,12 @@ Expected<LLVMState> LLVMState::Create(std::string TripleName,
   if (CpuName == "native")
     CpuName = std::string(sys::getHostCPUName());
 
+  if (CpuName.empty()) {
+    std::unique_ptr<MCSubtargetInfo> Empty_STI(
+        TheTarget->createMCSubtargetInfo(TripleName, "", ""));
+    CpuName = Empty_STI->getAllProcessorDescriptions().begin()->Key;
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topperc wrote:

This behavior seems weird. Is this guaranteed to be a basic CPU or could it be one with lots of features?

https://github.com/llvm/llvm-project/pull/89047