[llvm] ISel/AArch64: custom lower vector ISD::LRINT, ISD::LLRINT (PR #89035)

[Ramkumar Ramachandra via llvm-commits]

artagnon wrote:

The patch, as it is written, doesn't function with NEON, as I call `getPredicateForVector()`, which requires scalable vectors.

```
   4415
   4416	  // Finally, truncate the rounded floating point to an integer, rounding to
   4417	  // zero.
-> 4418	  SDValue Pred = getPredicateForVector(DAG, DL, ContainerVT);
   4419	  SDValue Undef = DAG.getUNDEF(ContainerVT);
   4420	  SDValue Truncated =
   4421	      DAG.getNode(AArch64ISD::FCVTZS_MERGE_PASSTHRU, DL, ContainerVT,
```

```
Assertion failed: (VT.isScalableVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && "Expected legal scalable vector!"), function getPredicateForScalableVector, file AArch64ISelLowering.cpp, line 26472.
```

I'm not very familiar with NEON, but do you think the patch can be made to work with it?

https://github.com/llvm/llvm-project/pull/89035