[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 17 03:36:13 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tools-llvm-exegesis
Author: None (AnastasiyaChernikova)
<details>
<summary>Changes</summary>
Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed.
Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@<!-- -->syntacore.com>
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@<!-- -->syntacore.com>
Co-authored-by: Dmitry Bushev <dmitry.bushev@<!-- -->syntacore.com>
Co-authored-by: Mark Goncharov <mark.goncharov@<!-- -->syntacore.com>
Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@<!-- -->syntacore.com>
---
Patch is 58.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/89047.diff
27 Files Affected:
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+3)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoF.td (+4)
- (added) llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s (+59)
- (added) llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s (+65)
- (added) llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s (+60)
- (added) llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s (+11)
- (added) llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s (+4)
- (modified) llvm/tools/llvm-exegesis/lib/Assembler.cpp (+9-1)
- (modified) llvm/tools/llvm-exegesis/lib/BenchmarkCode.h (+5)
- (modified) llvm/tools/llvm-exegesis/lib/CMakeLists.txt (+3)
- (modified) llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp (+8)
- (modified) llvm/tools/llvm-exegesis/lib/CodeTemplate.h (+6)
- (modified) llvm/tools/llvm-exegesis/lib/LlvmState.cpp (+6)
- (modified) llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp (+24-9)
- (modified) llvm/tools/llvm-exegesis/lib/MCInstrDescView.h (+12-1)
- (modified) llvm/tools/llvm-exegesis/lib/PerfHelper.h (+1-1)
- (added) llvm/tools/llvm-exegesis/lib/RISCV/CMakeLists.txt (+22)
- (added) llvm/tools/llvm-exegesis/lib/RISCV/RISCVCounters.cpp (+66)
- (added) llvm/tools/llvm-exegesis/lib/RISCV/RISCVCounters.h (+31)
- (added) llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp (+414)
- (modified) llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp (+54-8)
- (modified) llvm/tools/llvm-exegesis/lib/SnippetFile.cpp (+9-6)
- (modified) llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp (+12-1)
- (modified) llvm/tools/llvm-exegesis/lib/SnippetGenerator.h (+1)
- (modified) llvm/tools/llvm-exegesis/lib/Target.h (+21)
- (modified) llvm/tools/llvm-exegesis/llvm-exegesis.cpp (+53-15)
``````````diff
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 92f405b5f6acbf..9e83add7c4c3d9 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -299,6 +299,9 @@ enum OperandType : unsigned {
OPERAND_RVKRNUM_2_14,
OPERAND_SPIMM,
OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM,
+ // Operand is a 3-bit rounding mode, '111' indicates FRM register.
+ // Represents 'frm' argument passing to floating-point operations.
+ OPERAND_FRMARG,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index f9dadc6c0d4895..dddbeeddffa5b4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -509,7 +509,7 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
let isTerminator = 1;
}
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0, UseNamedOperandTable = 1 in {
class Load_ri<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
opcodestr, "$rd, ${imm12}(${rs1})">;
@@ -524,7 +524,7 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1, UseNamedOperandTable = 1 in {
class Store_rri<bits<3> funct3, string opcodestr>
: RVInstS<funct3, OPC_STORE, (outs),
(ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 7d89608de1223f..846f90e83df809 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -130,6 +130,8 @@ def frmarg : Operand<XLenVT> {
let ParserMatchClass = FRMArg;
let PrintMethod = "printFRMArg";
let DecoderMethod = "decodeFRMArg";
+ let OperandType = "OPERAND_FRMARG";
+ let OperandNamespace = "RISCVOp";
}
// Variants of the rounding mode operand that default to 'rne'. This is used
@@ -150,6 +152,8 @@ def frmarglegacy : Operand<XLenVT> {
let ParserMatchClass = FRMArgLegacy;
let PrintMethod = "printFRMArgLegacy";
let DecoderMethod = "decodeFRMArg";
+ let OperandType = "OPERAND_FRMARG";
+ let OperandNamespace = "RISCVOp";
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
new file mode 100644
index 00000000000000..e07452814c9096
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
@@ -0,0 +1,59 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOAND_D -mattr="+a" |& FileCheck --check-prefix=TEST1 %s
+
+TEST1: ---
+TEST1-NEXT: mode: latency
+TEST1-NEXT: key:
+TEST1-NEXT: instructions:
+TEST1-NEXT: - 'AMOAND_D [[RE01:X[0-9]+]] X10 [[RE01:X[0-9]+]]'
+TEST1-NEXT: config: ''
+TEST1-NEXT: register_initial_values:
+TEST1-NEXT: - '[[RE01:X[0-9]+]]=0x0'
+TEST1-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOADD_W -mattr="+a" |& FileCheck --check-prefix=TEST2 %s
+
+TEST2: ---
+TEST2-NEXT: mode: latency
+TEST2-NEXT: key:
+TEST2-NEXT: instructions:
+TEST2-NEXT: - 'AMOADD_W [[RE02:X[0-9]+]] X10 [[RE02:X[0-9]+]]'
+TEST2-NEXT: config: ''
+TEST2-NEXT: register_initial_values:
+TEST2-NEXT: - '[[RE02:X[0-9]+]]=0x0'
+TEST2-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOMAXU_D -mattr="+a" |& FileCheck --check-prefix=TEST3 %s
+
+TEST3: ---
+TEST3-NEXT: mode: latency
+TEST3-NEXT: key:
+TEST3-NEXT: instructions:
+TEST3-NEXT: - 'AMOMAXU_D [[RE03:X[0-9]+]] X10 [[RE03:X[0-9]+]]'
+TEST3-NEXT: config: ''
+TEST3-NEXT: register_initial_values:
+TEST3-NEXT: - '[[RE03:X[0-9]+]]=0x0'
+TEST3-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOMIN_W -mattr="+a" |& FileCheck --check-prefix=TEST4 %s
+
+TEST4: ---
+TEST4-NEXT: mode: latency
+TEST4-NEXT: key:
+TEST4-NEXT: instructions:
+TEST4-NEXT: - 'AMOMIN_W [[RE04:X[0-9]+]] X10 [[RE04:X[0-9]+]]'
+TEST4-NEXT: config: ''
+TEST4-NEXT: register_initial_values:
+TEST4-NEXT: - '[[RE04:X[0-9]+]]=0x0'
+TEST4-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOXOR_D -mattr="+a" |& FileCheck --check-prefix=TEST5 %s
+
+TEST5: ---
+TEST5-NEXT: mode: latency
+TEST5-NEXT: key:
+TEST5-NEXT: instructions:
+TEST5-NEXT: - 'AMOXOR_D [[RE05:X[0-9]+]] X10 [[RE05:X[0-9]+]]'
+TEST5-NEXT: config: ''
+TEST5-NEXT: register_initial_values:
+TEST5-NEXT: - '[[RE05:X[0-9]+]]=0x0'
+TEST5-LAST: ...
\ No newline at end of file
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
new file mode 100644
index 00000000000000..14a517750f3462
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
@@ -0,0 +1,65 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_ADDI -mattr=+c |& FileCheck --check-prefix=TEST1 %s
+
+TEST1: ---
+TEST1-NEXT: mode: latency
+TEST1-NEXT: key:
+TEST1-NEXT: instructions:
+TEST1-NEXT: - 'C_ADDI [[REG01:X[0-9]+]] [[RE02:X[0-9]+]] [[IMM0:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_ADDIW -mattr=+c |& FileCheck --check-prefix=TEST2 %s
+
+TEST2: ---
+TEST2-NEXT: mode: latency
+TEST2-NEXT: key:
+TEST2-NEXT: instructions:
+TEST2-NEXT: - 'C_ADDIW [[REG11:X[0-9]+]] [[RE12:X[0-9]+]] [[IMM1:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_ANDI -mattr=+c |& FileCheck --check-prefix=TEST3 %s
+
+TEST3: ---
+TEST3-NEXT: mode: latency
+TEST3-NEXT: key:
+TEST3-NEXT: instructions:
+TEST3-NEXT: - 'C_ANDI [[REG31:X[0-9]+]] [[REG32:X[0-9]+]] [[IMM3:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_SLLI -mattr=+c |& FileCheck --check-prefix=TEST4 %s
+
+TEST4: ---
+TEST4-NEXT: mode: latency
+TEST4-NEXT: key:
+TEST4-NEXT: instructions:
+TEST4-NEXT: - 'C_SLLI [[REG81:X[0-9]+]] [[REG82:X[0-9]+]] [[IMM8:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_SRAI -mattr=+c |& FileCheck --check-prefix=TEST5 %s
+
+TEST5: ---
+TEST5-NEXT: mode: latency
+TEST5-NEXT: key:
+TEST5-NEXT: instructions:
+TEST5-NEXT: - 'C_SRAI [[REG91:X[0-9]+]] [[REG92:X[0-9]+]] [[IMM9:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_SRLI -mattr=+c |& FileCheck --check-prefix=TEST6 %s
+
+TEST6: ---
+TEST6-NEXT: mode: latency
+TEST6-NEXT: key:
+TEST6-NEXT: instructions:
+TEST6-NEXT: - 'C_SRLI [[REG101:X[0-9]+]] [[REG102:X[0-9]+]] [[IMM10:i_0x[0-9]+]]'
+TEST6-LAST: ...
+
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_LD -mattr=+c |& FileCheck --check-prefix=TEST7 %s
+
+TEST7: ---
+TEST7-NEXT: mode: latency
+TEST7-NEXT: key:
+TEST7-NEXT: instructions:
+TEST7-NEXT: - 'C_LD [[REG61:X[0-9]+]] [[REG62:X[0-9]+]] [[IMM6:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_LW -mattr=+c |& FileCheck --check-prefix=TEST8 %s
+
+TEST8: ---
+TEST8-NEXT: mode: latency
+TEST8-NEXT: key:
+TEST8-NEXT: instructions:
+TEST8-NEXT: - 'C_LW [[REG71:X[0-9]+]] [[REG72:X[0-9]+]] [[IMM7:i_0x[0-9]+]]'
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
new file mode 100644
index 00000000000000..74ee7580c6054c
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
@@ -0,0 +1,60 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LD |& FileCheck --check-prefix=TEST1 %s
+
+TEST1: ---
+TEST1-NEXT: mode: latency
+TEST1-NEXT: key:
+TEST1-NEXT: instructions:
+TEST1-NEXT: - 'LD X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LW |& FileCheck --check-prefix=TEST2 %s
+
+TEST2: ---
+TEST2-NEXT: mode: latency
+TEST2-NEXT: key:
+TEST2-NEXT: instructions:
+TEST2-NEXT: - 'LW X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LH |& FileCheck --check-prefix=TEST3 %s
+
+TEST3: ---
+TEST3-NEXT: mode: latency
+TEST3-NEXT: key:
+TEST3-NEXT: instructions:
+TEST3-NEXT: - 'LH X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LWU |& FileCheck --check-prefix=TEST4 %s
+
+TEST4: ---
+TEST4-NEXT: mode: latency
+TEST4-NEXT: key:
+TEST4-NEXT: instructions:
+TEST4-NEXT: - 'LWU X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LBU |& FileCheck --check-prefix=TEST5 %s
+
+TEST5: ---
+TEST5-NEXT: mode: latency
+TEST5-NEXT: key:
+TEST5-NEXT: instructions:
+TEST5-NEXT: - 'LBU X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LUI |& FileCheck --check-prefix=TEST6 %s
+
+TEST6: LUI: No strategy found to make the execution serial
+
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LB |& FileCheck --check-prefix=TEST7 %s
+
+TEST7: ---
+TEST7-NEXT: mode: latency
+TEST7-NEXT: key:
+TEST7-NEXT: instructions:
+TEST7-NEXT: - 'LB X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LR_W_RL -mattr="+a" |& FileCheck --check-prefix=TEST8 %s
+
+TEST8: ---
+TEST8-NEXT: mode: latency
+TEST8-NEXT: key:
+TEST8-NEXT: instructions:
+TEST8-NEXT: - 'LR_W_RL X10 X10'
\ No newline at end of file
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s
new file mode 100644
index 00000000000000..b6ee3266cae6ca
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s
@@ -0,0 +1,11 @@
+# RUN: llvm-exegesis -mtriple=riscv64-unknown-linux -mode=latency --benchmark-phase=assemble-measured-code -mattr=+d -opcode-name=FADD_D |& FileCheck %s
+
+CHECK: ---
+CHECK-NEXT: mode: latency
+CHECK-NEXT: key:
+CHECK-NEXT: instructions:
+CHECK-NEXT: - 'FADD_D [[REG1:F[0-9]+_D]] [[REG2:F[0-9]+_D]] [[REG3:F[0-9]+_D]] i_0x7'
+CHECK-NEXT: config: ''
+CHECK-NEXT: register_initial_values:
+CHECK-DAG: - '[[REG1]]=0x0'
+CHECK-LAST: ...
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s
new file mode 100644
index 00000000000000..f0a114f648fa24
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s
@@ -0,0 +1,4 @@
+RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=LB -mtriple=riscv64-unknown-linux-gnu
+
+CHECK: Warning: Pre-assigned register prevented usage of self-aliasing strategy.
+
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 92ab3a96d91e6b..2908ea80d0e471 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -168,7 +168,15 @@ void BasicBlockFiller::addInstruction(const MCInst &Inst, const DebugLoc &DL) {
} else if (Op.isImm()) {
Builder.addImm(Op.getImm());
} else if (!Op.isValid()) {
- llvm_unreachable("Operand is not set");
+ std::string Message;
+ llvm::raw_string_ostream MessageOut(Message);
+ MessageOut << "Operand is not set: Instr: ";
+ Inst.dump_pretty(MessageOut, MCII->getName(Inst.getOpcode()));
+ MessageOut << "; OpIndex: " << OpIndex;
+ const MCOperandInfo &OperandInfo = MCID.operands()[OpIndex];
+ MessageOut << "; OpInfo.OperandType: "
+ << static_cast<uint32_t>(OperandInfo.OperandType);
+ report_fatal_error(Twine(Message));
} else {
llvm_unreachable("Not yet implemented");
}
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h b/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
index 1db8472e99f7c9..4d5fc241fde0d9 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
@@ -17,6 +17,11 @@
namespace llvm {
namespace exegesis {
+struct ScratchMemoryStore {
+ unsigned Reg;
+ unsigned Offset;
+};
+
// A collection of instructions that are to be assembled, executed and measured.
struct BenchmarkCode {
BenchmarkKey Key;
diff --git a/llvm/tools/llvm-exegesis/lib/CMakeLists.txt b/llvm/tools/llvm-exegesis/lib/CMakeLists.txt
index 414b49e5e021c2..bb201ed89e6c57 100644
--- a/llvm/tools/llvm-exegesis/lib/CMakeLists.txt
+++ b/llvm/tools/llvm-exegesis/lib/CMakeLists.txt
@@ -12,6 +12,9 @@ endif()
if (LLVM_TARGETS_TO_BUILD MATCHES "Mips")
list(APPEND LLVM_EXEGESIS_TARGETS "Mips")
endif()
+if(LLVM_TARGETS_TO_BUILD MATCHES "RISCV" OR LLVM_EXPERIMENTAL_TARGETS_TO_BUILD MATCHES "RISCV")
+ list(APPEND LLVM_EXEGESIS_TARGETS "RISCV")
+endif()
set(LLVM_EXEGESIS_TARGETS ${LLVM_EXEGESIS_TARGETS} PARENT_SCOPE)
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
index fd156ee01e7ce5..9b5bfe3196dcda 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
@@ -57,6 +57,14 @@ const MCOperand &InstructionTemplate::getValueFor(const Operand &Op) const {
return getValueFor(Instr->Variables[Op.getVariableIndex()]);
}
+MCOperand &InstructionTemplate::getValueFor(unsigned OpIdx) {
+ return getValueFor(Instr->Variables[OpIdx]);
+}
+
+const MCOperand &InstructionTemplate::getValueFor(unsigned OpIdx) const {
+ return getValueFor(Instr->Variables[OpIdx]);
+}
+
bool InstructionTemplate::hasImmediateVariables() const {
return any_of(Instr->Variables, [this](const Variable &Var) {
return Instr->getPrimaryOperand(Var).isImmediate();
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
index 7aca224302a1ff..85fcb4e908f017 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
@@ -35,6 +35,8 @@ struct InstructionTemplate {
const MCOperand &getValueFor(const Variable &Var) const;
MCOperand &getValueFor(const Operand &Op);
const MCOperand &getValueFor(const Operand &Op) const;
+ MCOperand &getValueFor(unsigned OpIdx);
+ const MCOperand &getValueFor(unsigned OpIdx) const;
bool hasImmediateVariables() const;
const Instruction &getInstr() const { return *Instr; }
ArrayRef<MCOperand> getVariableValues() const { return VariableValues; }
@@ -133,6 +135,10 @@ struct CodeTemplate {
// the pointer to this memory is passed in to the function.
unsigned ScratchSpacePointerInReg = 0;
+ // Require to pre-store value of a given register (fisrt)
+ // to scratch memory with given offset (second)
+ SmallVector<std::pair<unsigned, unsigned>, 2> PreinitScratchMemory;
+
#if defined(__GNUC__) && (defined(__clang__) || LLVM_GNUC_PREREQ(8, 0, 0))
// FIXME: GCC7 bug workaround. Drop #if after GCC7 no longer supported.
private:
diff --git a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
index 17d09a1ec0cf34..d387251a687e6a 100644
--- a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
+++ b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
@@ -45,6 +45,12 @@ Expected<LLVMState> LLVMState::Create(std::string TripleName,
if (CpuName == "native")
CpuName = std::string(sys::getHostCPUName());
+ if (CpuName.empty()) {
+ std::unique_ptr<MCSubtargetInfo> Empty_STI(
+ TheTarget->createMCSubtargetInfo(TripleName, "", ""));
+ CpuName = Empty_STI->getAllProcessorDescriptions().begin()->Key;
+ }
+
std::unique_ptr<MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, CpuName, ""));
assert(STI && "Unable to create subtarget info!");
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index 9c926d1fc61124..7705d9af4057e8 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -89,17 +89,17 @@ const BitVector *BitVectorCache::getUnique(BitVector &&BV) const {
return Entry.get();
}
-Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
- SmallVector<Operand, 8> Operands,
- SmallVector<Variable, 4> Variables,
- const BitVector *ImplDefRegs,
- const BitVector *ImplUseRegs,
- const BitVector *AllDefRegs,
- const BitVector *AllUseRegs)
+Instruction::Instruction(
+ const MCInstrDesc *Description, StringRef Name,
+ SmallVector<Operand, 8> Operands, SmallVector<Variable, 4> Variables,
+ const BitVector *ImplDefRegs, const BitVector *ImplUseRegs,
+ const BitVector *AllDefRegs, const BitVector *AllUseRegs,
+ const BitVector *MemoryRegs, const BitVector *NotMemoryRegs)
: Description(*Description), Name(Name), Operands(std::move(Operands)),
Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
- AllUseRegs(*AllUseRegs) {}
+ AllUseRegs(*AllUseRegs), MemoryRegs(*MemoryRegs),
+ NotMemoryRegs(*NotMemoryRegs) {}
std::unique_ptr<Instruction>
Instruction::create(const MCInstrInfo &InstrInfo,
@@ -166,6 +166,9 @@ Instruction::create(const MCInstrInfo &InstrInfo,
BitVector ImplUseRegs = RATC.emptyRegisters();
BitVector AllDefRegs = RATC.emptyRegisters();
BitVector AllUseRegs = RATC.emptyRegisters();
+ BitVector MemoryRegs = RATC.emptyRegisters();
+ BitVector NotMemoryRegs = RATC.emptyRegisters();
+
for (const auto &Op : Operands) {
if (Op.isReg()) {
const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
@@ -177,6 +180,10 @@ Instruction::create(const MCInstrInfo &InstrInfo,
ImplDefRegs |= AliasingBits;
if (Op.isUse() && Op.isImplicit())
ImplUseRegs |= AliasingBits;
+ if (Op.isUse() && Op.isMemory())
+ MemoryRegs |= AliasingBits;
+ if (Op.isUse() && !Op.isMemory())
+ NotMemoryRegs |= AliasingBits;
}
}
// Can't use make_unique because constructor is private.
@@ -185,7 +192,9 @@ Instruction::create(const MCInstrInfo &InstrInfo,
std::move(Variables), BVC.getUnique(std::move(ImplDefRegs)),
BVC.getUnique(std::move(ImplUseRegs)),
BVC.getUnique(std::move(AllDefRegs)),
- BVC.getUnique(std::move(AllUseRegs))));
+ BVC.getUnique(std::move(AllUseRegs)),
+ BVC.getUnique(std::move(MemoryRegs)),
+ BVC.getUnique(std::move(NotMemoryRegs))));
}
const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
@@ -240,6 +249,12 @@ bool Instruction::hasAliasingRegisters(
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/89047
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