[llvm] [AArch64][CodeGen] Fix illegal register aliasing bug for mops instrs (PR #88869)
Nashe Mncube via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 17 02:35:43 PDT 2024
https://github.com/nasherm updated https://github.com/llvm/llvm-project/pull/88869
>From 811b98b9c5f3a15ecb4b60a17eca61d851c18652 Mon Sep 17 00:00:00 2001
From: nasmnc01 <nashe.mncube at arm.com>
Date: Tue, 16 Apr 2024 10:34:09 +0100
Subject: [PATCH 1/3] [AArch64][CodeGen] Fix illegal register aliasing bug for
mops instrs
A bug was found where mops instructions were being generated that
aliased the source and size registers. This is unpredictable behaviour.
This patch usess the earlyclobber constraint on the input source register
so that it doesn't alias with the size register. Also a test is introduced
which tests affected instructions can't violate this constraint.
Change-Id: I34debad21fe8a5f6c33e159b43a1e13d092764a0
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 +-
.../MC/AArch64/armv9.3a-mops-register-aliasing.s | 15 +++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/AArch64/armv9.3a-mops-register-aliasing.s
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e1624f70185e1e..3bf90778363c6c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -9486,7 +9486,7 @@ let Predicates = [HasMOPS], Defs = [NZCV], Size = 12, mayStore = 1 in {
let mayLoad = 0 in {
def MOPSMemorySetPseudo : Pseudo<(outs GPR64common:$Rd_wb, GPR64:$Rn_wb),
(ins GPR64common:$Rd, GPR64:$Rn, GPR64:$Rm),
- [], "$Rd = $Rd_wb,$Rn = $Rn_wb">, Sched<[]>;
+ [], "$Rd = $Rd_wb,$Rn = $Rn_wb, at earlyclobber $Rn_wb">, Sched<[]>;
}
}
let Predicates = [HasMOPS, HasMTE], Defs = [NZCV], Size = 12, mayLoad = 0, mayStore = 1 in {
diff --git a/llvm/test/MC/AArch64/armv9.3a-mops-register-aliasing.s b/llvm/test/MC/AArch64/armv9.3a-mops-register-aliasing.s
new file mode 100644
index 00000000000000..109b33857a9d2d
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.3a-mops-register-aliasing.s
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple aarch64 -mattr=+mops < %s 2>&1 | FileCheck %s
+
+ setp [x0]!, x1!, x1
+ setm [x0]!, x1!, x1
+ sete [x0]!, x1!, x1
+
+// CHECK: error: invalid SET instruction, source and size registers are the same
+// CHECK-NEXT: setp [x0]!, x1!, x1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: invalid SET instruction, source and size registers are the same
+// CHECK-NEXT: setm [x0]!, x1!, x1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: invalid SET instruction, source and size registers are the same
+// CHECK-NEXT: sete [x0]!, x1!, x1
+// CHECK-NEXT: ^
>From 18b1188b271840bc19ca1d4b5b0afb1040298156 Mon Sep 17 00:00:00 2001
From: nasmnc01 <nashe.mncube at arm.com>
Date: Tue, 16 Apr 2024 15:56:16 +0100
Subject: [PATCH 2/3] Adding mops intrinsic register alias test
Change-Id: Ifc34f656cc4fb33ad8a46ea80b4896f8d0f2ac60
---
.../CodeGen/AArch64/mops-register-alias.ll | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/mops-register-alias.ll
diff --git a/llvm/test/CodeGen/AArch64/mops-register-alias.ll b/llvm/test/CodeGen/AArch64/mops-register-alias.ll
new file mode 100644
index 00000000000000..eeb7559421f62e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/mops-register-alias.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -O1 -mtriple=aarch64-none-linux-gnu -mattr=+mops -o - %s | FileCheck %s
+
+define void @call_memset_intrinsic() #0 {
+; CHECK-LABEL: call_memset_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: .cfi_def_cfa_offset 80
+; CHECK-NEXT: movi v0.16b, #64
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: mov w9, #64 // =0x40
+; CHECK-NEXT: mov w10, #64 // =0x40
+; CHECK-NEXT: add x8, x8, #64
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: stp q0, q0, [sp, #32]
+; CHECK-NEXT: setp [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
+; CHECK-NOT: setp [x{{[0-9]+}}]!, x[[REG:[0-9]+]]!, x[[REG]]
+; CHECK-NEXT: setm [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
+; CHECK-NOT: setm [x{{[0-9]+}}]!, x[[REG:[0-9]+]]!, x[[REG]]
+; CHECK-NEXT: sete [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
+; CHECK-NOT: sete [x{{[0-9]+}}]!, x[[REG:[0-9]+]]!, x[[REG]]
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
+entry:
+
+ %V0 = alloca [65 x i8], align 1
+ call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(64) %V0, i8 64, i64 64, i1 false)
+ %add.ptr = getelementptr inbounds i8, ptr %V0, i64 64
+ call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(64) %add.ptr, i8 64, i64 64, i1 false)
+ ret void
+}
+
+attributes #0 = { "target-cpu"="generic" "target-features"="+mops,+strict-align,+v9.3a" }
>From ca2fc5e27cbaf132c788e89355ef843623fc7036 Mon Sep 17 00:00:00 2001
From: nasmnc01 <nashe.mncube at arm.com>
Date: Wed, 17 Apr 2024 10:34:32 +0100
Subject: [PATCH 3/3] Terser mops register alias test
Change-Id: I68edcdf4414d8a21b2267e7593997f0276ad6e54
---
llvm/test/CodeGen/AArch64/mops-register-alias.ll | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/mops-register-alias.ll b/llvm/test/CodeGen/AArch64/mops-register-alias.ll
index eeb7559421f62e..855ab959c4e76b 100644
--- a/llvm/test/CodeGen/AArch64/mops-register-alias.ll
+++ b/llvm/test/CodeGen/AArch64/mops-register-alias.ll
@@ -1,26 +1,14 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -O1 -mtriple=aarch64-none-linux-gnu -mattr=+mops -o - %s | FileCheck %s
define void @call_memset_intrinsic() #0 {
; CHECK-LABEL: call_memset_intrinsic:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: .cfi_def_cfa_offset 80
-; CHECK-NEXT: movi v0.16b, #64
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: mov w9, #64 // =0x40
-; CHECK-NEXT: mov w10, #64 // =0x40
-; CHECK-NEXT: add x8, x8, #64
-; CHECK-NEXT: stp q0, q0, [sp]
-; CHECK-NEXT: stp q0, q0, [sp, #32]
-; CHECK-NEXT: setp [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
+; CHECK: setp [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
; CHECK-NOT: setp [x{{[0-9]+}}]!, x[[REG:[0-9]+]]!, x[[REG]]
; CHECK-NEXT: setm [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
; CHECK-NOT: setm [x{{[0-9]+}}]!, x[[REG:[0-9]+]]!, x[[REG]]
; CHECK-NEXT: sete [x{{[0-9]+}}]!, x{{[0-9]+}}!, x{{[0-9]+}}
; CHECK-NOT: sete [x{{[0-9]+}}]!, x[[REG:[0-9]+]]!, x[[REG]]
-; CHECK-NEXT: add sp, sp, #80
-; CHECK-NEXT: ret
entry:
%V0 = alloca [65 x i8], align 1
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