[llvm] bbd64c4 - [RISCV] Add coverage for strength reduction of mul as 2^N - 2^M
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 16 11:46:34 PDT 2024
Author: Philip Reames
Date: 2024-04-16T11:46:27-07:00
New Revision: bbd64c4ddf08be468ab4eb4c161e28bdab6808bb
URL: https://github.com/llvm/llvm-project/commit/bbd64c4ddf08be468ab4eb4c161e28bdab6808bb
DIFF: https://github.com/llvm/llvm-project/commit/bbd64c4ddf08be468ab4eb4c161e28bdab6808bb.diff
LOG: [RISCV] Add coverage for strength reduction of mul as 2^N - 2^M
Added:
Modified:
llvm/test/CodeGen/RISCV/mul.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index af341dbaadeabd..364e8c7b38dacc 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -465,6 +465,192 @@ define i32 @mulhu_constant(i32 %a) nounwind {
ret i32 %4
}
+define i32 @muli32_p14(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p14:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 14
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p14:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 14
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p14:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 14
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p14:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 14
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 14
+ ret i32 %1
+}
+
+define i32 @muli32_p28(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p28:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 28
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p28:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 28
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p28:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 28
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p28:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 28
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 28
+ ret i32 %1
+}
+
+define i32 @muli32_p30(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p30:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 30
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p30:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 30
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 30
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p30:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 30
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 30
+ ret i32 %1
+}
+
+define i32 @muli32_p56(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p56:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 56
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p56:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 56
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p56:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 56
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p56:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 56
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 56
+ ret i32 %1
+}
+
+define i32 @muli32_p60(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p60:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 60
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p60:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 60
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p60:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 60
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p60:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 60
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 60
+ ret i32 %1
+}
+
+define i32 @muli32_p62(i32 %a) nounwind {
+; RV32I-LABEL: muli32_p62:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a1, 62
+; RV32I-NEXT: tail __mulsi3
+;
+; RV32IM-LABEL: muli32_p62:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a1, 62
+; RV32IM-NEXT: mul a0, a0, a1
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muli32_p62:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a1, 62
+; RV64I-NEXT: call __muldi3
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muli32_p62:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a1, 62
+; RV64IM-NEXT: mulw a0, a0, a1
+; RV64IM-NEXT: ret
+ %1 = mul i32 %a, 62
+ ret i32 %1
+}
+
define i32 @muli32_p65(i32 %a) nounwind {
; RV32I-LABEL: muli32_p65:
; RV32I: # %bb.0:
@@ -600,6 +786,8 @@ define i64 @muli64_p63(i64 %a) nounwind {
ret i64 %1
}
+
+
define i32 @muli32_m63(i32 %a) nounwind {
; RV32I-LABEL: muli32_m63:
; RV32I: # %bb.0:
@@ -1145,10 +1333,10 @@ define i128 @muli128_m3840(i128 %a) nounwind {
; RV32I-NEXT: sltu a7, a6, a4
; RV32I-NEXT: sub t0, t1, t0
; RV32I-NEXT: mv t1, a7
-; RV32I-NEXT: beq a5, a3, .LBB30_2
+; RV32I-NEXT: beq a5, a3, .LBB36_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t1, a5, a3
-; RV32I-NEXT: .LBB30_2:
+; RV32I-NEXT: .LBB36_2:
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sltu a1, a2, t1
; RV32I-NEXT: sub a1, t0, a1
@@ -1261,10 +1449,10 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32I-NEXT: slli t0, a1, 6
; RV32I-NEXT: or a7, t0, a7
; RV32I-NEXT: mv t0, a5
-; RV32I-NEXT: beq a1, a7, .LBB31_2
+; RV32I-NEXT: beq a1, a7, .LBB37_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t0, a1, a7
-; RV32I-NEXT: .LBB31_2:
+; RV32I-NEXT: .LBB37_2:
; RV32I-NEXT: srli t1, a1, 26
; RV32I-NEXT: slli t2, a6, 6
; RV32I-NEXT: or t1, t2, t1
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