[llvm] [AMDGPU] Fix debug line table for MSG_DEALLOC_VGPRS optimization (PR #88924)

[Emma Pilkington via llvm-commits]

https://github.com/epilk updated https://github.com/llvm/llvm-project/pull/88924

>From f2da128ce8de5d6f6a272ecc64b7285fa43809a1 Mon Sep 17 00:00:00 2001
From: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: Tue, 16 Apr 2024 11:28:09 -0400
Subject: [PATCH 1/3] [AMDGPU] Fix debug line table for MSG_DEALLOC_VGPRS
 optimization

---
 llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp   |  5 ++-
 .../CodeGen/AMDGPU/release-vgprs-dbg-loc.mir  | 40 +++++++++++++++++++
 2 files changed, 43 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 556ec3e231ff19..36de5b89af0280 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -2665,10 +2665,11 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
   // instructions.
   for (MachineInstr *MI : ReleaseVGPRInsts) {
     if (ST->requiresNopBeforeDeallocVGPRs()) {
-      BuildMI(*MI->getParent(), MI, DebugLoc(), TII->get(AMDGPU::S_NOP))
+      BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::S_NOP))
           .addImm(0);
     }
-    BuildMI(*MI->getParent(), MI, DebugLoc(), TII->get(AMDGPU::S_SENDMSG))
+    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
+            TII->get(AMDGPU::S_SENDMSG))
         .addImm(AMDGPU::SendMsg::ID_DEALLOC_VGPRS_GFX11Plus);
     Modified = true;
   }
diff --git a/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir b/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
new file mode 100644
index 00000000000000..4741cb982d4e09
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O2 -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-insert-waitcnts -verify-machineinstrs -o - %s | FileCheck %s
+
+# Verify that si-insert-waitcnts copies debug locations from the s_endpgm to the
+# "dealloc vgprs" s_sendmsg. If these are not present, the debugger will be
+# unable to break at the end of the shader.
+
+--- |
+  define amdgpu_ps void @test() !dbg !5 { ret void, !dbg !8 }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.debugify = !{!2, !3}
+  !llvm.module.flags = !{!4}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+  !1 = !DIFile(filename: "t.ll", directory: "/")
+  !2 = !{i32 1}
+  !3 = !{i32 0}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = distinct !DISubprogram(name: "test", linkageName: "test", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+  !6 = !DISubroutineType(types: !7)
+  !7 = !{}
+  !8 = !DILocation(line: 1, column: 1, scope: !5)
+...
+
+---
+name:            test
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test
+    ; CHECK: GLOBAL_STORE_DWORD undef renamable $vgpr0_vgpr1, killed renamable $vgpr1, 0, 4, implicit $exec
+    ; CHECK-NEXT: S_NOP 0, debug-location !8
+    ; CHECK-NEXT: S_SENDMSG 3, implicit $exec, implicit $m0, debug-location !8
+    ; CHECK-NEXT: S_ENDPGM 0, debug-location !8
+    GLOBAL_STORE_DWORD undef renamable $vgpr0_vgpr1, killed renamable $vgpr1, 0, 4, implicit $exec
+    S_ENDPGM 0, debug-location !8
+...
+

>From 6692558a68e949a3f32a3d4eaeb38058f77e2ab8 Mon Sep 17 00:00:00 2001
From: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: Tue, 16 Apr 2024 12:42:21 -0400
Subject: [PATCH 2/3] Update llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
 llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir b/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
index 4741cb982d4e09..fb77e832f28cc3 100644
--- a/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
+++ b/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O2 -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-insert-waitcnts -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc  -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-insert-waitcnts  -o - %s | FileCheck %s
 
 # Verify that si-insert-waitcnts copies debug locations from the s_endpgm to the
 # "dealloc vgprs" s_sendmsg. If these are not present, the debugger will be

>From c057427b2638218962ef15fe01c43576c603acc2 Mon Sep 17 00:00:00 2001
From: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: Tue, 16 Apr 2024 12:46:22 -0400
Subject: [PATCH 3/3] Update llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
 llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir b/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
index fb77e832f28cc3..e50ee11fef51c0 100644
--- a/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
+++ b/llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc  -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-insert-waitcnts  -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-insert-waitcnts -o - %s | FileCheck %s
 
 # Verify that si-insert-waitcnts copies debug locations from the s_endpgm to the
 # "dealloc vgprs" s_sendmsg. If these are not present, the debugger will be