[llvm] [SelectionDAG] Fold (icmp eq/ne (shift X, C), 0) -> (icmp eq/ne X, 0) (PR #88801)

[Björn Pettersson via llvm-commits]

================
@@ -586,6 +586,7 @@ define i1 @add_ultcmp_i32_i16(i32 %x) nounwind {
 ; RV64I-NEXT:    lui a1, 8
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srliw a0, a0, 16
+; RV64I-NEXT:    slli a0, a0, 16
----------------
bjope wrote:

Looks like RISCV isn't optimizing
```
      t41: i64 = and t32, Constant:i64<4294901760>
    t42: i64 = setcc t41, Constant:i64<0>, setne:ch
```
as good as
```
      t43: i64 = and t32, Constant:i64<4294967295>
      t38: i64 = srl t43, Constant:i64<16>
    t39: i64 = setcc t38, Constant:i64<0>, setne:ch
```
It does fold SRL+AND into a single srliw. But the AND is lowered into srliw+slli. Problem is that it would need to understand that the using setcc doesn't care about where the bits go.
@asb / @topperc / @michaelmaitland : Is RISCV lacking ISel patterns for setcc+"and with shifted mask"?

https://github.com/llvm/llvm-project/pull/88801