[llvm] [RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (PR #88295)

[Luke Lau via llvm-commits]

lukel97 wrote:

@BeMg I looked at some of the diffs on SPEC CPU 2017 more closely, there are only two extra spills and at least one of them is a scalar spill, so I'm not worried about it.

I can see some differences with regards to scheduling though, it mainly seems to be where we're no longer able to move instructions above a load or store, here's one such example:

```diff
--- build.a/External/SPEC/CFP2017rate/526.blender_r/CMakeFiles/526.blender_r.dir/root/cpu2017/benchspec/CPU/526.blender_
r/src/blender/source/blender/blenkernel/intern/seqeffects.s     2024-04-10 16:43:45.181903504 +0000
+++ build.b/External/SPEC/CFP2017rate/526.blender_r/CMakeFiles/526.blender_r.dir/root/cpu2017/benchspec/CPU/526.blender_
r/src/blender/source/blender/blenkernel/intern/seqeffects.s     2024-04-10 16:43:56.813588028 +0000
@@ -9253,30 +9253,30 @@
	vsetivli        zero, 1, e8, mf8, ta, ma
	vmv.v.i v8, 3
	vsetivli        zero, 8, e32, m2, ta, mu
-       vmv1r.v v0, v8
-       vfmerge.vfm     v14, v12, fa3, v0
-       vfmv.v.f        v10, fa4
-       vfmerge.vfm     v16, v10, fa5, v0
 .Lpcrel_hi169:
	auipc   t0, %pcrel_hi(.LCPI57_0)
	addi    t0, t0, %pcrel_lo(.Lpcrel_hi169)
-       vle16.v v18, (t0)
+       vle16.v v14, (t0)
+       vmv1r.v v0, v8
+       vfmerge.vfm     v16, v12, fa3, v0
+       vfmv.v.f        v10, fa4
+       vfmerge.vfm     v18, v10, fa5, v0
+       vrgatherei16.vv v10, v18, v14
```

As you say, I think this is caused by an invisible vsetvli after the vle16.v thats coalesced in the postpass, but temporarily exists before pre-regalloc occurs. So hopefully not an issue if we finish moving the rest of RISCVInsertVSETVLI to post-regalloc.

https://github.com/llvm/llvm-project/pull/88295