[llvm] [RISCV] Expand mul to shNadd x, (slli x, c) in DAGCombine (PR #88524)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

This patch causes llc to generate more instructions than before: https://github.com/dtcxzyw/llvm-codegen-benchmark/commit/2973ba786de69a73026473874d08937415702d63

An example: https://godbolt.org/z/x376qeGEx
```
define i64 @test(i32 signext %x, i32 signext %y) {
  %sub = sub i32 %x, %y
  %ext = zext i32 %sub to i64
  %res = mul nuw nsw i64 %ext, 24
  ret i64 %res
}
```

Before:
```
test:                                   # @test
        subw    a0, a0, a1
        slli.uw a0, a0, 3
        sh1add  a0, a0, a0
        ret
```

After:
```
test:                                   # @test
        subw    a0, a0, a1
        zext.w  a1, a0
        sh1add.uw       a0, a0, a1
        slli    a0, a0, 3
        ret
```


https://github.com/llvm/llvm-project/pull/88524