[llvm] [RISCV] Add FeatureStdExtI to all CPUs in RISCVProcessors.td. NFC (PR #88805)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp approved this pull request.

> I'm planning to move all extension information to RISCVFeatures.td and have tablegen create the tables for RISCVISAInfo.cpp. This requires making the creation of RISCVTargetParserDef.inc in tablegen independent of RISCVISAInfo.cpp. So we need an accurate extension list for CPUs in tablegen.

I was thinking about the same thing but I didn't finish it. I think we can generate profile march string too. :-)

https://github.com/llvm/llvm-project/pull/88805