[llvm] [DAG] Introduce generic shl_add node [NFC] (PR #88791)

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git-clang-format --diff b7b183371b54a2c4b5d2a39c594d3967a7384cb8 4dafa09b6fd78a46cd803e3dda47ec4fc16dcbbf -- llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.h
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diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 59385c8bc2..0e8297fdb0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3524,8 +3524,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
   case ISD::SHL_ADD:
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
-    Known = KnownBits::computeForAddSub(true, false, false,
-        KnownBits::shl(Known, Known2),
+    Known = KnownBits::computeForAddSub(
+        true, false, false, KnownBits::shl(Known, Known2),
         computeKnownBits(Op.getOperand(2), DemandedElts, Depth + 1));
     break;
   case ISD::FSHL:
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 50e271bde0..49baebee62 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2556,8 +2556,7 @@ bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
     assert(CN->getZExtValue() == 1 || CN->getZExtValue() == 2 ||
            CN->getZExtValue() == 3);
     if (AM.BaseType == X86ISelAddressMode::RegBase &&
-        AM.Base_Reg.getNode() == nullptr &&
-        AM.IndexReg.getNode() == nullptr) {
+        AM.Base_Reg.getNode() == nullptr && AM.IndexReg.getNode() == nullptr) {
       AM.Scale = unsigned(2 << (CN->getZExtValue() - 1));
 
       if (N.getOperand(0) == N.getOperand(2)) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 477c368c22..749d9f7378 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36843,7 +36843,8 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
 
   Known.resetAll();
   switch (Opc) {
-  default: break;
+  default:
+    break;
   case X86ISD::SETCC:
     Known.Zero.setBitsFrom(1);
     break;
@@ -46900,7 +46901,7 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
 static SDValue createMulImm(uint64_t MulAmt, SDValue N, SelectionDAG &DAG,
                             EVT VT, const SDLoc &DL) {
   assert(MulAmt == 3 || MulAmt == 5 || MulAmt == 9);
-  SDValue ShAmt = DAG.getConstant(Log2_64(MulAmt-1), DL, MVT::i8);
+  SDValue ShAmt = DAG.getConstant(Log2_64(MulAmt - 1), DL, MVT::i8);
   return DAG.getNode(ISD::SHL_ADD, DL, VT, N, ShAmt, N);
 }
 

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https://github.com/llvm/llvm-project/pull/88791