[llvm] [SelectionDAG] Fix and improve TargetLowering::SimplifySetCC (PR #87646)

[via llvm-commits]

AtariDreams wrote:

> > I'm just asking if this is a miscompile or not just to make sure
> 
> No, that particular diff is not due to any miscompile. The DAG used to be something like this:
> 
> ```
>     t24: i32,ch = load<(load (s16) from %ir.y + 1, align 1, basealign 8), zext from i16> t0, t23, undef:i32
>     t21: i1 = setcc t24, Constant:i32<0>, setne:ch
> ```
> 
> and now we get
> 
> ```
>     t24: i32,ch = load<(load (s16) from %ir.y + 1, align 1, basealign 8), zext from i16> t0, t23, undef:i32
>     t26: i32 = shl t24, Constant:i32<8>
>     t21: i1 = setcc t26, Constant:i32<0>, setne:ch
> ```
> 
> So it just shifts out bits that are known to be zero before the compare. Without deeper knowledge about ARM, the result would be equivalent here.

I just looked at the diff, and the code being generated is not equivalent at all.

https://github.com/llvm/llvm-project/pull/87646