[llvm] [AMDGPU] In VectorLegalizer::Expand, if UnrollVectorOp returns Load, … (PR #88475)

[via llvm-commits]

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@@ -1159,8 +1159,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
   }
 
   SDValue Unrolled = DAG.UnrollVectorOp(Node);
-  for (unsigned I = 0, E = Unrolled->getNumValues(); I != E; ++I)
-    Results.push_back(Unrolled.getValue(I));
+  const LoadSDNode *Ld = dyn_cast<LoadSDNode>(Unrolled.getNode());
+  if (Ld)
+    Results.push_back(Unrolled);
+  else
+    for (unsigned I = 0, E = Unrolled->getNumValues(); I != E; ++I)
+      Results.push_back(Unrolled.getValue(I));
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choikwa wrote:

Thank you all for the feedback. I took @topperc 's suggestion and replicated the lowering logic in the newest update.

https://github.com/llvm/llvm-project/pull/88475