[clang] [llvm] [AArch64] Add intrinsics for 16-bit non-widening FMLA/FMLS (PR #88553)

[via llvm-commits]

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+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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CarolineConcatto wrote:

If you change these prototypes to be sme2 like the ACLE we need to change these run lines to be sme2

https://github.com/llvm/llvm-project/pull/88553