[llvm] [DAG] Fold build_vector(build_pair()) patterns. (PR #88261)

[Philip Reames via llvm-commits]

================
@@ -3560,10 +3560,12 @@ define <2 x i64> @mgather_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %passthr
 ; RV32ZVE32F-NEXT:    lw a4, 4(a1)
 ; RV32ZVE32F-NEXT:    lw a1, 0(a1)
 ; RV32ZVE32F-NEXT:  .LBB43_5: # %else2
-; RV32ZVE32F-NEXT:    sw a3, 0(a0)
-; RV32ZVE32F-NEXT:    sw a2, 4(a0)
-; RV32ZVE32F-NEXT:    sw a1, 8(a0)
-; RV32ZVE32F-NEXT:    sw a4, 12(a0)
+; RV32ZVE32F-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
----------------
preames wrote:

Looking at there, I'm not too worried by these changes.

These are all around the lowering of an <N x i64> return value for a configuration where the largest supported element type is i32.  (i.e. legalization.)  While this is a supported configuration, it's not a particularly widely used one.

@topperc It surprises me that the ABI would use a by reference return here rather than treating the register as simply containing bits and returning the vector register. We should probably check to make sure this matches the newly approved ABI, and possibly raise a question about it regardless.

We could possibly explore a combine which converted a store(build_vector) into a set of scalar stores, but that's a very delicate transform from a costing perspective and I'm a bit hesitant to do that.  





https://github.com/llvm/llvm-project/pull/88261