[llvm] [ARM][AArch64] autogenerate header file for TargetParser from Target tablegen files (PR #88378)
David Spickett via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 15 02:45:58 PDT 2024
================
@@ -0,0 +1,67 @@
+//===- ARMTargetDefEmitter.cpp - Generate data about ARM Architectures ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend exports information about CPUs, FPUs, architectures,
+// and features into a common format that can be used by both TargetParser and
+// the ARM backend.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/StringSet.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+using namespace llvm;
+
+static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+ OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
+
+ // Look through all SubtargetFeature defs with the given FieldName, and
+ // collect the set of all Values that that FieldName is set to.
+ auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+ llvm::StringSet<> Set;
+ for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
+ if (Rec->getValueAsString("FieldName") == FieldName) {
+ Set.insert(Rec->getValueAsString("Value"));
+ }
+ }
+ return Set;
+ };
+
+ // The ARMProcFamilyEnum values are initialised by SubtargetFeature defs
+ // which set the ARMProcFamily field. We can generate the enum from these defs
+ // which look like this:
+ //
+ // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
+ // "Cortex-A5 ARM processors", []>;
+ OS << "#ifndef ARM_PROCESSOR_FAMILY\n"
+ << "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
+ << "#endif\n\n";
+ const StringSet<> ARMProcFamilyVals =
+ gatherSubtargetFeatureFieldValues("ARMProcFamily");
+ for (const StringRef &Family : ARMProcFamilyVals.keys()) {
+ OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
+ }
+ OS << "\n#undef ARM_PROCESSOR_FAMILY\n";
+ OS << "\n";
+
+ OS << "#ifndef ARM_ARCHITECTURE\n"
+ << "#define ARM_ARCHITECTURE(ENUM)\n"
+ << "#endif\n\n";
+ // This should correspond to instances of the Architecture tablegen class.
+ const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+ for (const StringRef &Arch : ARMArchVals.keys()) {
+ OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
+ }
+ OS << "\n#undef ARM_ARCHITECTURE\n";
+ OS << "\n";
----------------
DavidSpickett wrote:
If clang-format agrees, you could do this as:
```
OS << "......"
<< "\n";
```
https://github.com/llvm/llvm-project/pull/88378
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