[llvm] [GlobalISel][AArch64] Add LLRINT support (PR #88702)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 15 02:14:16 PDT 2024
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/88702
This hooks up G_INTRINSIC_LLRINT instructions, very similar to the lrint nodes that already exist. On AArch64 they are treated the same as lrint with the default return types.
>From 667969e6fe49bb8f9c0b27255e2a15faee10426d Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 15 Apr 2024 10:06:58 +0100
Subject: [PATCH] [GlobalISel][AArch64] Add LLRINT support
This hooks up G_LLRINT instructions, very similar to the lrint nodes that
already exist. On AArch64 they are treated the same as lrint with the default
return types.
---
llvm/include/llvm/Support/TargetOpcodes.def | 3 +
llvm/include/llvm/Target/GenericOpcodes.td | 6 ++
.../Target/GlobalISel/SelectionDAGCompat.td | 1 +
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 6 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +-
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 1 +
.../AArch64/GlobalISel/arm64-irtranslator.ll | 10 ++
.../AArch64/GlobalISel/legalize-llrint.mir | 98 +++++++++++++++++++
.../GlobalISel/legalizer-info-validation.mir | 4 +
llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll | 2 +
llvm/test/CodeGen/AArch64/llrint-conv.ll | 58 +++++++----
12 files changed, 170 insertions(+), 23 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 5765926d6d93d3..cb98f96af522f7 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -351,6 +351,9 @@ HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
/// INTRINSIC round to integer intrinsic.
HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT)
+/// INTRINSIC long round to integer intrinsic.
+HANDLE_TARGET_OPCODE(G_INTRINSIC_LLRINT)
+
/// INTRINSIC roundeven intrinsic.
HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index d0f471eb29b6fd..e8cf8fcb647f45 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1089,6 +1089,12 @@ def G_INTRINSIC_LRINT : GenericInstruction {
let hasSideEffects = false;
}
+def G_INTRINSIC_LLRINT : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src);
+ let hasSideEffects = false;
+}
+
def G_INTRINSIC_ROUNDEVEN : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index dd4e7d790bc6b3..8fa0e4b86d6dc9 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -157,6 +157,7 @@ def : GINodeEquiv<G_INTRINSIC_TRUNC, ftrunc>;
def : GINodeEquiv<G_INTRINSIC_ROUND, fround>;
def : GINodeEquiv<G_INTRINSIC_ROUNDEVEN, froundeven>;
def : GINodeEquiv<G_INTRINSIC_LRINT, lrint>;
+def : GINodeEquiv<G_INTRINSIC_LLRINT, llrint>;
def : GINodeEquiv<G_FCOPYSIGN, fcopysign>;
def : GINodeEquiv<G_SMIN, smin>;
def : GINodeEquiv<G_SMAX, smax>;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 9b4575f7f34d47..0b6aae3759756f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1955,6 +1955,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
return TargetOpcode::G_PTRMASK;
case Intrinsic::lrint:
return TargetOpcode::G_INTRINSIC_LRINT;
+ case Intrinsic::llrint:
+ return TargetOpcode::G_INTRINSIC_LLRINT;
// FADD/FMUL require checking the FMF, so are handled elsewhere.
case Intrinsic::vector_reduce_fmin:
return TargetOpcode::G_VECREDUCE_FMIN;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 20a7fa25351994..92d5ad70f29861 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -474,6 +474,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
RTLIBCASE(ROUNDEVEN_F);
case TargetOpcode::G_INTRINSIC_LRINT:
RTLIBCASE(LRINT_F);
+ case TargetOpcode::G_INTRINSIC_LLRINT:
+ RTLIBCASE(LLRINT_F);
}
llvm_unreachable("Unknown libcall function");
}
@@ -1061,7 +1063,8 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
return Status;
break;
}
- case TargetOpcode::G_INTRINSIC_LRINT: {
+ case TargetOpcode::G_INTRINSIC_LRINT:
+ case TargetOpcode::G_INTRINSIC_LLRINT: {
LLT LLTy = MRI.getType(MI.getOperand(1).getReg());
unsigned Size = LLTy.getSizeInBits();
Type *HLTy = getFloatTypeForLLT(Ctx, LLTy);
@@ -2661,6 +2664,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_INTRINSIC_LRINT:
+ case TargetOpcode::G_INTRINSIC_LLRINT:
case TargetOpcode::G_IS_FPCLASS:
Observer.changingInstr(MI);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 661ea151d1a0ce..85dd0f2eb192d9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -262,7 +262,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.minScalar(0, s32)
.scalarize(0);
- getActionDefinitionsBuilder(G_INTRINSIC_LRINT)
+ getActionDefinitionsBuilder({G_INTRINSIC_LRINT, G_INTRINSIC_LLRINT})
.legalFor({{s64, MinFPScalar}, {s64, s32}, {s64, s64}})
.libcallFor({{s64, s128}})
.minScalarOrElt(1, MinFPScalar);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index d39de770eaf16e..44f5603e76ff12 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -830,6 +830,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_INTRINSIC_LRINT:
+ case TargetOpcode::G_INTRINSIC_LLRINT:
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
break;
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index a131f35e66d033..a61931b898aea5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1385,6 +1385,16 @@ define i32 @test_intrinsic_lrint(float %a) {
ret i32 %res
}
+declare i32 @llvm.llrint.i32.f32(float)
+define i32 @test_intrinsic_llrint(float %a) {
+; CHECK-LABEL: name: test_intrinsic_llrint
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LLRINT [[A]]
+; CHECK: $w0 = COPY [[RES]]
+ %res = call i32 @llvm.llrint.i32.f32(float %a)
+ ret i32 %res
+}
+
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
new file mode 100644
index 00000000000000..f77649b793951d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
@@ -0,0 +1,98 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: testmsws
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$s0' }
+body: |
+ bb.1:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: testmsws
+ ; CHECK: liveins: $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[INTRINSIC_LLRINT]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ %0:_(s32) = COPY $s0
+ %1:_(s64) = G_INTRINSIC_LLRINT %0(s32)
+ %2:_(s32) = G_TRUNC %1(s64)
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: testmsxs
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$s0' }
+body: |
+ bb.1:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: testmsxs
+ ; CHECK: liveins: $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[INTRINSIC_LLRINT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %0:_(s32) = COPY $s0
+ %1:_(s64) = G_INTRINSIC_LLRINT %0(s32)
+ $x0 = COPY %1(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: testmswd
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$d0' }
+body: |
+ bb.1:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: testmswd
+ ; CHECK: liveins: $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[INTRINSIC_LLRINT]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_INTRINSIC_LLRINT %0(s64)
+ %2:_(s32) = G_TRUNC %1(s64)
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: testmsxd
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$d0' }
+body: |
+ bb.1:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: testmsxd
+ ; CHECK: liveins: $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s64)
+ ; CHECK-NEXT: $x0 = COPY [[INTRINSIC_LLRINT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_INTRINSIC_LLRINT %0(s64)
+ $x0 = COPY %1(s64)
+ RET_ReallyLR implicit $x0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 0793f3983c8e57..098726b0a980df 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -156,6 +156,10 @@
# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_INTRINSIC_LLRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_INTRINSIC_ROUNDEVEN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll b/llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
index 1adbbab76abf52..7e28c863b07a9a 100644
--- a/llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
+++ b/llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK-NOFP16
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK-FP16
define i16 @testmhhs(half %x) {
; CHECK-NOFP16-LABEL: testmhhs:
diff --git a/llvm/test/CodeGen/AArch64/llrint-conv.ll b/llvm/test/CodeGen/AArch64/llrint-conv.ll
index fa11b007eeb3dd..3a6396d120f791 100644
--- a/llvm/test/CodeGen/AArch64/llrint-conv.ll
+++ b/llvm/test/CodeGen/AArch64/llrint-conv.ll
@@ -1,59 +1,75 @@
-; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s
-; CHECK-LABEL: testmsws:
-; CHECK: frintx [[REG:s[0-9]]], s0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK: ret
define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs x0, s0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxs:
-; CHECK: frintx [[REG:s[0-9]]], s0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs x0, s0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
ret i64 %0
}
-; CHECK-LABEL: testmswd:
-; CHECK: frintx [[REG:d[0-9]]], d0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK: ret
define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx d0, d0
+; CHECK-NEXT: fcvtzs x0, d0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxd:
-; CHECK: frintx [[REG:d[0-9]]], d0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK-nEXT: ret
define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx d0, d0
+; CHECK-NEXT: fcvtzs x0, d0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)
ret i64 %0
}
-; CHECK-LABEL: testmswl:
-; CHECK: bl llrintl
define i32 @testmswl(fp128 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl llrintl
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsll:
-; CHECK: b llrintl
define i64 @testmsll(fp128 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: b llrintl
entry:
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
ret i64 %0
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