[llvm] [RISCV] Don't use V0 directly in patterns (PR #88496)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> Thanks for pointing me to the patch! I do have a vague impression that someone may has tried this before.

Singleton register classes are a bad idea (i.e. VMV0 should not be defined). You're going to have an endless stream of register allocation failures in ever more obscure scenarios

https://github.com/llvm/llvm-project/pull/88496