[llvm] [RISCV] Make more vector pseudos commutable (PR #88379)

[Pengcheng Wang via llvm-commits]

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@@ -2743,10 +2750,11 @@ multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint =
   }
 }
 
-multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
+multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
+                                bit Commutable = 0> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defm "" : VPseudoBinaryV_VV<m, Constraint>,
+    defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
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wangpc-pp wrote:

Yeah, it may make sense. I added this argument just to match existed code.

https://github.com/llvm/llvm-project/pull/88379