[llvm] [RISCV][ISel] Combine scalable vector fadd/fsub/fmul with fp extend. (PR #88615)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 14 23:56:55 PDT 2024
================
@@ -13597,6 +13599,13 @@ struct NodeExtensionHelper {
case RISCVISD::VZEXT_VL:
case RISCVISD::FP_EXTEND_VL:
return OrigOperand.getOperand(0);
+ case ISD::SPLAT_VECTOR: {
+ SDValue Op = OrigOperand.getOperand(0);
+ if (Op.getOpcode() == ISD::FP_EXTEND)
+ return Op;
----------------
lukel97 wrote:
How does this work for fixed length float splats currently if we didn't already handle `RISCVISD::VFMV_V_F_VL`? Since in #81248 it looks like we emit vfwadd.vf
https://github.com/llvm/llvm-project/pull/88615
More information about the llvm-commits
mailing list