[llvm] [RISCV] Don't use V0 directly in patterns (PR #88496)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> > @lukel97 didn't you try this previously?
> 
> Yeah, the issue I ran into was due to MachineCSE constraining operands to VMV0, which sometimes meant we had an earlyclobber constraint on an instruction with two VMV0s, e.g.:
> 
> ```
> early-clobber %res:vr = PseudoVMSEQ_VV_M2_MASK %mask:vmv0(tied-def 0), ..., %mask:vmv0, ...
> ```
> 
> So regalloc would fail because it can't choose two separate registers from VMV0: #75347
> 
> I discussed this offline with @MatzeB and @arsenm and I think the consensus was that singleton register classes weren't really a thing on other targets and the conventional thing to do would be to use a virtual reg to physical reg copy.
> 
> But looking at the premerge CI for this PR, the crash doesn't seem to be appearing? Specifically I think this affected the compare instructions i.e. vmseq. Did something change with MachineCSE in the meantime? Digging out my old patch it seems to be doing the same thing:

Thanks for pointing me to the patch! I do have a vague impression that someone may has tried this before.

Actually I just found the same `error: ran out of registers during register allocation` issue. I just tried your changes of `MachineCSE` and it can fix part of the problem. There are still some errors like `llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll`. I will have a look.

>From the result of this patch (decrease of MactherTable and some potential optimizations), I think it worths doing such change. WDYT?

https://github.com/llvm/llvm-project/pull/88496