[llvm] [SelectionDAG] Propagate Disjoint flag. (PR #88370)

[via llvm-commits]

https://github.com/fengfeng09 updated https://github.com/llvm/llvm-project/pull/88370

>From 0cd1acfb1e4fb40923569693d08acfe91d6e8df0 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 00:29:12 +0800
Subject: [PATCH 1/2] Precommit test for propagate disjoint.NFC

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 .../CodeGen/X86/propagate-disjoint-in-shl-or.ll | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll

diff --git a/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll
new file mode 100644
index 00000000000000..3c1d231460c7dd
--- /dev/null
+++ b/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64 %s -start-before=x86-isel -o - | FileCheck %s
+
+define i32 @add_shl_or_disjoint(i32 %x) {
+; CHECK-LABEL: add_shl_or_disjoint:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    leal (,%rdi,4), %eax
+; CHECK-NEXT:    orl $-1069531068, %eax # imm = 0xC0404044
+; CHECK-NEXT:    addl $1234567890, %eax # imm = 0x499602D2
+; CHECK-NEXT:    retq
+  %or = or disjoint i32 %x, 4027584529
+  %shl = shl i32 %or, 2
+  %add = add i32 %shl, 1234567890
+  ret i32 %add
+}
+

>From 061c76e769ac04f3e9992e371dcf983501434b0b Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 00:32:59 +0800
Subject: [PATCH 2/2] [SelectionDAG] Propagate Disjoint flag.

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp         | 3 ++-
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp      | 3 ++-
 llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll | 4 +---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8fe074666a3dc9..c7bb98425d9935 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9530,7 +9530,8 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) {
   SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT);
   SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC);
   SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1);
-  return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2);
+  return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2,
+                     LogicOp->getFlags());
 }
 
 /// Handle transforms common to the three shifts, when the shift amount is a
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 409d66adfd67d1..169d4a6f08de73 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -544,7 +544,8 @@ bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
     if (!C.isSubsetOf(DemandedBits)) {
       EVT VT = Op.getValueType();
       SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT);
-      SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
+      SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC,
+                                      Op->getFlags());
       return TLO.CombineTo(Op, NewOp);
     }
 
diff --git a/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll
index 3c1d231460c7dd..e38840f3e46106 100644
--- a/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll
+++ b/llvm/test/CodeGen/X86/propagate-disjoint-in-shl-or.ll
@@ -5,9 +5,7 @@ define i32 @add_shl_or_disjoint(i32 %x) {
 ; CHECK-LABEL: add_shl_or_disjoint:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT:    leal (,%rdi,4), %eax
-; CHECK-NEXT:    orl $-1069531068, %eax # imm = 0xC0404044
-; CHECK-NEXT:    addl $1234567890, %eax # imm = 0x499602D2
+; CHECK-NEXT:    leal 165036822(,%rdi,4), %eax
 ; CHECK-NEXT:    retq
   %or = or disjoint i32 %x, 4027584529
   %shl = shl i32 %or, 2