[llvm] 342aa3e - [LegalizeTypes][RISCV] Support scalable vectors in SplitVecRes_BITCAST/SplitVecOp_BITCAST. (#88590)
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Sat Apr 13 20:54:13 PDT 2024
Author: Craig Topper
Date: 2024-04-13T20:54:09-07:00
New Revision: 342aa3eb23992ad742d22ef0e0d8821a9b29de3e
URL: https://github.com/llvm/llvm-project/commit/342aa3eb23992ad742d22ef0e0d8821a9b29de3e
DIFF: https://github.com/llvm/llvm-project/commit/342aa3eb23992ad742d22ef0e0d8821a9b29de3e.diff
LOG: [LegalizeTypes][RISCV] Support scalable vectors in SplitVecRes_BITCAST/SplitVecOp_BITCAST. (#88590)
Instead of bitcasting to a scalar integer, try to split the other vector
type that is legal. We already handle the case where both types need to
be split.
Fixes #88576
Added:
llvm/test/CodeGen/RISCV/rvv/pr88576.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 1f6e0097f31ab4..8776d89f4c5bd9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1388,6 +1388,13 @@ void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
report_fatal_error("Scalarization of scalable vectors is not supported.");
}
+ if (LoVT.isScalableVector()) {
+ auto [InLo, InHi] = DAG.SplitVectorOperand(N, 0);
+ Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, InLo);
+ Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, InHi);
+ return;
+ }
+
// In the general case, convert the input to an integer and split it by hand.
EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
@@ -3259,16 +3266,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
// For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
// end up being split all the way down to individual components. Convert the
// split pieces into integers and reassemble.
+ EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi);
+ SDLoc dl(N);
+
+ if (ResVT.isScalableVector()) {
+ auto [LoVT, HiVT] = DAG.GetSplitDestVTs(ResVT);
+ Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
+ Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
+ }
+
Lo = BitConvertToInteger(Lo);
Hi = BitConvertToInteger(Hi);
if (DAG.getDataLayout().isBigEndian())
std::swap(Lo, Hi);
- return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
- JoinIntegers(Lo, Hi));
+ return DAG.getNode(ISD::BITCAST, dl, ResVT, JoinIntegers(Lo, Hi));
}
SDValue DAGTypeLegalizer::SplitVecOp_INSERT_SUBVECTOR(SDNode *N,
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr88576.ll b/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
new file mode 100644
index 00000000000000..b6e0d1e2ff4ae7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
+
+define i1 @foo(<vscale x 16 x i8> %x, i64 %y) {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: bltu a0, a2, .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: addi sp, sp, -80
+; CHECK-NEXT: .cfi_def_cfa_offset 80
+; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset ra, -8
+; CHECK-NEXT: .cfi_offset s0, -16
+; CHECK-NEXT: addi s0, sp, 80
+; CHECK-NEXT: .cfi_def_cfa s0, 0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: sub sp, sp, a2
+; CHECK-NEXT: andi sp, sp, -64
+; CHECK-NEXT: addi a2, sp, 64
+; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vs8r.v v24, (a1)
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a2)
+; CHECK-NEXT: lbu a0, 0(a0)
+; CHECK-NEXT: addi sp, s0, -80
+; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 80
+; CHECK-NEXT: ret
+ %a = bitcast <vscale x 16 x i8> %x to <vscale x 128 x i1>
+ %b = extractelement <vscale x 128 x i1> %a, i64 %y
+ ret i1 %b
+}
+
+define i8 @bar(<vscale x 128 x i1> %x, i64 %y) {
+; CHECK-LABEL: bar:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v1, v8
+; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v0, a0
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %a = bitcast <vscale x 128 x i1> %x to <vscale x 16 x i8>
+ %b = extractelement <vscale x 16 x i8> %a, i64 %y
+ ret i8 %b
+}
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