[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michal Terepeta via llvm-commits]

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@@ -307,44 +307,68 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX
+        : VPseudoVC_X<OpClass, RS1Class>,
+          Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
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michalt wrote:

Ok, I finally took another look at this. Right now I don't think my team would need `SchedRead`/`ReadAdvance`s for any of these instructions. But I'm happy to add them if you think that's important. So let me know what you think! (also, would you be ok to add it in a separate PR?) Thanks! 🙂 

https://github.com/llvm/llvm-project/pull/86093