[llvm] [RISCV] Don't use V0 directly in patterns (PR #88496)

[Min-Yih Hsu via llvm-commits]

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@@ -116,8 +123,8 @@ bool RISCVFoldMasks::convertVMergeToVMv(MachineInstr &MI) const {
                                            TRI->lookThruCopyLike(FalseReg, MRI))
     return false;
 
-  assert(MI.getOperand(4).isReg() && MI.getOperand(4).getReg() == RISCV::V0);
-  if (!isAllOnesMask(V0Defs.lookup(&MI)))
+  // assert(MI.getOperand(4).isReg() && MI.getOperand(4).getReg() == RISCV::V0);
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mshockwave wrote:

please remove this line.

https://github.com/llvm/llvm-project/pull/88496