[llvm] [M68k] Add support for MOVEQ instruction (PR #88542)
Peter Lafreniere via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 12 10:38:23 PDT 2024
https://github.com/n8pjl created https://github.com/llvm/llvm-project/pull/88542
Add support for the moveq instruction, which is both faster and smaller
(1/2 to 1/3 the size) than a move with immediate to register.
This change introduces the instruction, along with a set of
pseudoinstructions to handle immediate moves to a register that is
lowered post-RA.
Pseudos are used as moveq can only write to the full register, which makes
matching i8 and i16 immediate loads difficult in tablegen. Furthermore,
selecting moveq before RA constrains that immediate to be moved into a data
register, which may not be optimal.
The bulk of this change are fixes to existing tests, which cover the new
functionality sufficiently.
>From 130fb5190ed657ee8b93cc9ecf38f271fe667983 Mon Sep 17 00:00:00 2001
From: Peter Lafreniere <peter at n8pjl.ca>
Date: Fri, 12 Apr 2024 13:26:32 -0400
Subject: [PATCH] [M68k] Add support for MOVEQ instruction
Add support for the moveq instruction, which is both faster and smaller
(1/2 to 1/3 the size) than a move with immediate to register.
This change introduces the instruction, along with a set of
pseudoinstructions to handle immediate moves to a register that is
lowered post-RA.
Pseudos are used as moveq can only write to the full register, which makes
matching i8 and i16 immediate loads difficult in tablegen. Furthermore,
selecting moveq before RA constrains that immediate to be moved into a data
register, which may not be optimal.
The bulk of this change are fixes to existing tests, which cover the new
functionality sufficiently.
---
llvm/lib/Target/M68k/M68kExpandPseudo.cpp | 7 ++++
llvm/lib/Target/M68k/M68kInstrData.td | 41 +++++++++++++++++--
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 34 +++++++++++++++
llvm/lib/Target/M68k/M68kInstrInfo.h | 3 ++
.../CodeGen/M68k/Arith/add-with-overflow.ll | 2 +-
llvm/test/CodeGen/M68k/Arith/add.ll | 4 +-
llvm/test/CodeGen/M68k/Arith/bitwise.ll | 6 +--
.../CodeGen/M68k/Arith/divide-by-constant.ll | 14 +++----
llvm/test/CodeGen/M68k/Arith/imul.ll | 16 ++++----
.../CodeGen/M68k/Arith/smul-with-overflow.ll | 12 +++---
.../CodeGen/M68k/Arith/sub-with-overflow.ll | 10 ++---
llvm/test/CodeGen/M68k/Arith/sub.ll | 2 +-
.../CodeGen/M68k/Arith/umul-with-overflow.ll | 6 +--
llvm/test/CodeGen/M68k/CConv/c-call.ll | 6 +--
llvm/test/CodeGen/M68k/CConv/fastcc-call.ll | 12 +++---
.../CodeModel/medium-pie-global-access.ll | 4 +-
.../M68k/CodeModel/small-pie-global-access.ll | 4 +-
llvm/test/CodeGen/M68k/Control/cmp.ll | 26 ++++++------
llvm/test/CodeGen/M68k/Control/long-setcc.ll | 4 +-
llvm/test/CodeGen/M68k/Control/setcc.ll | 6 +--
llvm/test/CodeGen/M68k/PR57660.ll | 2 +-
llvm/test/CodeGen/M68k/gcc_except_table.ll | 2 +-
llvm/test/CodeGen/M68k/link-unlnk.ll | 4 +-
llvm/test/MC/Disassembler/M68k/data.txt | 6 +++
llvm/test/MC/M68k/Data/Classes/MxMove_RI.s | 3 ++
25 files changed, 162 insertions(+), 74 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
index 7fcc65beaa653b..c7fdd7d7c35023 100644
--- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
+++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
@@ -80,6 +80,13 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
default:
return false;
+ case M68k::MOVI8di:
+ return TII->ExpandMOVI(MIB, MVT::i8);
+ case M68k::MOVI16ri:
+ return TII->ExpandMOVI(MIB, MVT::i16);
+ case M68k::MOVI32ri:
+ return TII->ExpandMOVI(MIB, MVT::i32);
+
case M68k::MOVXd16d8:
return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
case M68k::MOVXd32d8:
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index fa7e7aa0ed4619..dc777a933e2786 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -19,7 +19,7 @@
///
/// Pseudo:
///
-/// MOVSX [x] MOVZX [x] MOVX [x]
+/// MOVI [x] MOVSX [x] MOVZX [x] MOVX [x]
///
/// Map:
///
@@ -165,11 +165,12 @@ foreach AM = MxMoveSupportedAMs in {
} // foreach AM
// R <- I
+// No pattern, as all immediate -> register moves are matched to the MOVI pseudo
class MxMove_RI<MxType TYPE, string DST_REG, MxMoveEncoding ENC,
MxImmOpBundle SRC = !cast<MxImmOpBundle>("MxOp"#TYPE.Size#"AddrMode_i"),
MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG)>
: MxMove<TYPE.Prefix, (outs DST.Op:$dst), (ins SRC.Op:$src),
- [(set TYPE.VT:$dst, SRC.ImmPat:$src)], ENC>;
+ [(null_frag)], ENC>;
foreach REG = ["r", "a", "d"] in {
foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
@@ -242,6 +243,24 @@ def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst),
def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst),
(MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>;
+//===----------------------------------------------------------------------===//
+// MOVEQ
+//===----------------------------------------------------------------------===//
+
+/// ------------+---------+---+-----------------------
+/// F E D C | B A 9 | 8 | 7 6 5 4 3 2 1 0
+/// ------------+---------+---+-----------------------
+/// 0 1 1 1 | REG | 0 | DATA
+/// ------------+---------+---+-----------------------
+
+// No pattern, as all immediate -> register moves are matched to the MOVI pseudo
+let Defs = [CCR] in
+def MOVQ : MxInst<(outs MxDRD32:$dst), (ins Mxi8imm:$imm),
+ "moveq\t$imm, $dst",
+ [(null_frag)]> {
+ let Inst = (descend 0b0111, (operand "$dst", 3), 0b0, (operand "$imm", 8));
+}
+
//===----------------------------------------------------------------------===//
// MOVEM
//
@@ -496,7 +515,23 @@ class MxPseudoMove_RR<MxType DST, MxType SRC, list<dag> PAT = []>
class MxPseudoMove_RM<MxType DST, MxOperand SRCOpd, list<dag> PAT = []>
: MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), PAT>;
-}
+
+
+// These Pseudos handle loading immediates to registers.
+// They are expanded post-RA into either move or moveq instructions,
+// depending on size, destination register class, and immediate value.
+// This is done with pseudoinstructions in order to not constrain RA to
+// data registers if moveq matches.
+class MxPseudoMove_DI<MxType TYPE>
+ : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.IOp:$src),
+ [(set TYPE.ROp:$dst, imm:$src)]>;
+
+// i8 imm -> reg can always be converted to moveq,
+// but we still emit a pseudo for consistency.
+def MOVI8di : MxPseudoMove_DI<MxType8d>;
+def MOVI16ri : MxPseudoMove_DI<MxType16r>;
+def MOVI32ri : MxPseudoMove_DI<MxType32r>;
+} // let Defs = [CCR]
/// This group of Pseudos is analogues to the real x86 extending moves, but
/// since M68k does not have those we need to emulate. These instructions
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index d56fef9e9029af..338db45782c961 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -346,6 +346,40 @@ void M68kInstrInfo::AddZExt(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(And), Reg).addReg(Reg).addImm(Mask);
}
+// Convert MOVI to MOVQ if the target is a data register and the immediate
+// fits in a sign-extended i8, otherwise emit a plain MOV.
+bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const {
+ Register Reg = MIB->getOperand(0).getReg();
+ int64_t Imm = MIB->getOperand(1).getImm();
+ bool IsAddressReg = false;
+
+ const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID);
+ const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID);
+ const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID);
+
+ if (AR16->contains(Reg) || AR32->contains(Reg))
+ IsAddressReg = true;
+
+ LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to ");
+
+ if (MVTSize == MVT::i8 || (!IsAddressReg && Imm >= -128 && Imm <= 127)) {
+ LLVM_DEBUG(dbgs() << "MOVEQ\n");
+
+ // We need to assign to the full register to make IV happy
+ Register SReg =
+ MVTSize == MVT::i32 ? Reg : Register(RI.getMatchingMegaReg(Reg, DR32));
+ assert(SReg && "No viable MEGA register available");
+
+ MIB->setDesc(get(M68k::MOVQ));
+ MIB->getOperand(0).setReg(SReg);
+ } else {
+ LLVM_DEBUG(dbgs() << "MOVE\n");
+ MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri));
+ }
+
+ return true;
+}
+
bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst,
MVT MVTSrc) const {
unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index 577967f2fdfc97..d1e1e1cd99987b 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -302,6 +302,9 @@ class M68kInstrInfo : public M68kGenInstrInfo {
void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
DebugLoc DL, unsigned Reg, MVT From, MVT To) const;
+ /// Move immediate to register
+ bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const;
+
/// Move across register classes without extension
bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const;
diff --git a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
index bd5e593edb33d8..70479b0b3ec65c 100644
--- a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
@@ -35,7 +35,7 @@ define fastcc i1 @test6(i32 %v1, i32 %v2, ptr %X) nounwind {
; CHECK-NEXT: ; %bb.1: ; %normal
; CHECK-NEXT: move.l #0, (%a0)
; CHECK-NEXT: .LBB1_2: ; %carry
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll
index 281751e3e183c7..a9eb0bb815b088 100644
--- a/llvm/test/CodeGen/M68k/Arith/add.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add.ll
@@ -43,7 +43,7 @@ define fastcc void @test3(ptr inreg %a) nounwind {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l (%a0), %d0
-; CHECK-NEXT: move.l #0, %d1
+; CHECK-NEXT: moveq #0, %d1
; CHECK-NEXT: move.l #-2147483648, %d2
; CHECK-NEXT: add.l (4,%a0), %d2
; CHECK-NEXT: addx.l %d0, %d1
@@ -64,7 +64,7 @@ define fastcc void @test4(ptr inreg %a) nounwind {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l (%a0), %d0
-; CHECK-NEXT: move.l #0, %d1
+; CHECK-NEXT: moveq #0, %d1
; CHECK-NEXT: move.l #128, %d2
; CHECK-NEXT: add.l (4,%a0), %d2
; CHECK-NEXT: addx.l %d0, %d1
diff --git a/llvm/test/CodeGen/M68k/Arith/bitwise.ll b/llvm/test/CodeGen/M68k/Arith/bitwise.ll
index 70e4dd42bfb6de..74fc543a5fb856 100644
--- a/llvm/test/CodeGen/M68k/Arith/bitwise.ll
+++ b/llvm/test/CodeGen/M68k/Arith/bitwise.ll
@@ -242,7 +242,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: add.l #-32, %d1
; CHECK-NEXT: bmi .LBB18_1
; CHECK-NEXT: ; %bb.2:
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: bra .LBB18_3
; CHECK-NEXT: .LBB18_1:
; CHECK-NEXT: move.l %d2, %d0
@@ -301,7 +301,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: add.l #-32, %d3
; CHECK-NEXT: bmi .LBB19_5
; CHECK-NEXT: ; %bb.4:
-; CHECK-NEXT: move.l #31, %d2
+; CHECK-NEXT: moveq #31, %d2
; CHECK-NEXT: .LBB19_5:
; CHECK-NEXT: asr.l %d2, %d0
; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -322,7 +322,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: add.l #-32, %d0
; CHECK-NEXT: bmi .LBB20_1
; CHECK-NEXT: ; %bb.2:
-; CHECK-NEXT: move.l #0, %d1
+; CHECK-NEXT: moveq #0, %d1
; CHECK-NEXT: bra .LBB20_3
; CHECK-NEXT: .LBB20_1:
; CHECK-NEXT: move.l %d2, %d1
diff --git a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
index 834dfe1c26f08f..fcc8dd3e7662e1 100644
--- a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
+++ b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
@@ -40,7 +40,7 @@ define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) {
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: muls #171, %d0
-; CHECK-NEXT: move.w #9, %d1
+; CHECK-NEXT: moveq #9, %d1
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
@@ -58,7 +58,7 @@ define signext i16 @test4(i16 signext %x) nounwind {
; CHECK-NEXT: muls #1986, %d0
; CHECK-NEXT: asr.l #8, %d0
; CHECK-NEXT: asr.l #8, %d0
-; CHECK-NEXT: move.w #15, %d1
+; CHECK-NEXT: moveq #15, %d1
; CHECK-NEXT: move.w %d0, %d2
; CHECK-NEXT: lsr.w %d1, %d2
; CHECK-NEXT: add.w %d2, %d0
@@ -94,7 +94,7 @@ define signext i16 @test6(i16 signext %x) nounwind {
; CHECK-NEXT: muls #26215, %d0
; CHECK-NEXT: asr.l #8, %d0
; CHECK-NEXT: asr.l #8, %d0
-; CHECK-NEXT: move.w #15, %d1
+; CHECK-NEXT: moveq #15, %d1
; CHECK-NEXT: move.w %d0, %d2
; CHECK-NEXT: lsr.w %d1, %d2
; CHECK-NEXT: asr.w #2, %d0
@@ -128,7 +128,7 @@ define i8 @test8(i8 %x) nounwind {
; CHECK-NEXT: lsr.b #1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: muls #211, %d0
-; CHECK-NEXT: move.w #13, %d1
+; CHECK-NEXT: moveq #13, %d1
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
; CHECK-NEXT: rts
@@ -143,7 +143,7 @@ define i8 @test9(i8 %x) nounwind {
; CHECK-NEXT: lsr.b #2, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: muls #71, %d0
-; CHECK-NEXT: move.w #11, %d1
+; CHECK-NEXT: moveq #11, %d1
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
; CHECK-NEXT: rts
@@ -156,11 +156,11 @@ define i32 @testsize1(i32 %x) minsize nounwind {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
-; CHECK-NEXT: move.l #31, %d1
+; CHECK-NEXT: moveq #31, %d1
; CHECK-NEXT: move.l (8,%sp), %d0
; CHECK-NEXT: move.l %d0, %d2
; CHECK-NEXT: asr.l %d1, %d2
-; CHECK-NEXT: move.l #27, %d1
+; CHECK-NEXT: moveq #27, %d1
; CHECK-NEXT: lsr.l %d1, %d2
; CHECK-NEXT: add.l %d2, %d0
; CHECK-NEXT: asr.l #5, %d0
diff --git a/llvm/test/CodeGen/M68k/Arith/imul.ll b/llvm/test/CodeGen/M68k/Arith/imul.ll
index f53568395c29b2..a1846e4d51bd2e 100644
--- a/llvm/test/CodeGen/M68k/Arith/imul.ll
+++ b/llvm/test/CodeGen/M68k/Arith/imul.ll
@@ -19,7 +19,7 @@ define i64 @mul4_64(i64 %A) {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -8
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
-; CHECK-NEXT: move.l #30, %d0
+; CHECK-NEXT: moveq #30, %d0
; CHECK-NEXT: move.l (12,%sp), %d1
; CHECK-NEXT: move.l %d1, %d2
; CHECK-NEXT: lsr.l %d0, %d2
@@ -38,7 +38,7 @@ define i32 @mul4096_32(i32 %A) {
; CHECK-LABEL: mul4096_32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #12, %d1
+; CHECK-NEXT: moveq #12, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsl.l %d1, %d0
; CHECK-NEXT: rts
@@ -53,11 +53,11 @@ define i64 @mul4096_64(i64 %A) {
; CHECK-NEXT: suba.l #8, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -12
; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
-; CHECK-NEXT: move.l #20, %d0
+; CHECK-NEXT: moveq #20, %d0
; CHECK-NEXT: move.l (16,%sp), %d1
; CHECK-NEXT: move.l %d1, %d2
; CHECK-NEXT: lsr.l %d0, %d2
-; CHECK-NEXT: move.l #12, %d3
+; CHECK-NEXT: moveq #12, %d3
; CHECK-NEXT: move.l (12,%sp), %d0
; CHECK-NEXT: lsl.l %d3, %d0
; CHECK-NEXT: or.l %d2, %d0
@@ -73,7 +73,7 @@ define i32 @mulmin4096_32(i32 %A) {
; CHECK-LABEL: mulmin4096_32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #12, %d1
+; CHECK-NEXT: moveq #12, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsl.l %d1, %d0
; CHECK-NEXT: neg.l %d0
@@ -89,11 +89,11 @@ define i64 @mulmin4096_64(i64 %A) {
; CHECK-NEXT: suba.l #8, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -12
; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
-; CHECK-NEXT: move.l #20, %d0
+; CHECK-NEXT: moveq #20, %d0
; CHECK-NEXT: move.l (16,%sp), %d1
; CHECK-NEXT: move.l %d1, %d2
; CHECK-NEXT: lsr.l %d0, %d2
-; CHECK-NEXT: move.l #12, %d3
+; CHECK-NEXT: moveq #12, %d3
; CHECK-NEXT: move.l (12,%sp), %d0
; CHECK-NEXT: lsl.l %d3, %d0
; CHECK-NEXT: or.l %d2, %d0
@@ -258,7 +258,7 @@ define i32 @mul0_32(i32 %A) {
; CHECK-LABEL: mul0_32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
%mul = mul i32 %A, 0
ret i32 %mul
diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
index 5bd4d5d48bc859..10a797f1344141 100644
--- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
@@ -24,7 +24,7 @@ entry:
define zeroext i8 @smul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp {
; CHECK-LABEL: smul_i8_no_ovf:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #42, %d0
+; CHECK-NEXT: moveq #42, %d0
; CHECK-NEXT: rts
entry:
%smul = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 %b)
@@ -70,7 +70,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB3_1: ; %normal
@@ -78,7 +78,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -108,7 +108,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB4_2: ; %normal
@@ -116,7 +116,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -155,7 +155,7 @@ define i32 @test4(i32 %a, i32 %b) nounwind readnone {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: move.l (8,%sp), %d0
; CHECK-NEXT: add.l (4,%sp), %d0
-; CHECK-NEXT: move.l #4, %d1
+; CHECK-NEXT: moveq #4, %d1
; CHECK-NEXT: muls.l %d1, %d0
; CHECK-NEXT: rts
entry:
diff --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
index 8d47c7ebf7e56f..be3223156986e6 100644
--- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
@@ -19,7 +19,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB0_1: ; %normal
@@ -27,7 +27,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -56,7 +56,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB1_1: ; %normal
@@ -64,7 +64,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -85,7 +85,7 @@ carry:
define i1 @func3(i32 %x) nounwind {
; CHECK-LABEL: func3:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #-1, %d0
+; CHECK-NEXT: moveq #-1, %d0
; CHECK-NEXT: add.l (4,%sp), %d0
; CHECK-NEXT: svs %d0
; CHECK-NEXT: rts
diff --git a/llvm/test/CodeGen/M68k/Arith/sub.ll b/llvm/test/CodeGen/M68k/Arith/sub.ll
index fff3601000dfa8..16d0498b3dbbc6 100644
--- a/llvm/test/CodeGen/M68k/Arith/sub.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sub.ll
@@ -7,7 +7,7 @@ define i32 @test1(i32 %x) {
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d1
; CHECK-NEXT: eori.l #31, %d1
-; CHECK-NEXT: move.l #32, %d0
+; CHECK-NEXT: moveq #32, %d0
; CHECK-NEXT: sub.l %d1, %d0
; CHECK-NEXT: rts
%xor = xor i32 %x, 31
diff --git a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
index fd128a3e52bd3e..3314e65399c431 100644
--- a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
@@ -24,7 +24,7 @@ entry:
define zeroext i8 @umul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp {
; CHECK-LABEL: umul_i8_no_ovf:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #42, %d0
+; CHECK-NEXT: moveq #42, %d0
; CHECK-NEXT: rts
entry:
%umul = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 %b)
@@ -59,7 +59,7 @@ declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
define i1 @a(i32 %x) nounwind {
; CHECK-LABEL: a:
; CHECK: ; %bb.0:
-; CHECK-NEXT: move.l #3, %d0
+; CHECK-NEXT: moveq #3, %d0
; CHECK-NEXT: move.l (4,%sp), %d1
; CHECK-NEXT: mulu.l %d0, %d1
; CHECK-NEXT: svs %d0
@@ -90,7 +90,7 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: move.l (8,%sp), %d0
; CHECK-NEXT: add.l (4,%sp), %d0
-; CHECK-NEXT: move.l #4, %d1
+; CHECK-NEXT: moveq #4, %d1
; CHECK-NEXT: mulu.l %d1, %d0
; CHECK-NEXT: rts
entry:
diff --git a/llvm/test/CodeGen/M68k/CConv/c-call.ll b/llvm/test/CodeGen/M68k/CConv/c-call.ll
index a9638eec6a3138..badd4e31f37d18 100644
--- a/llvm/test/CodeGen/M68k/CConv/c-call.ll
+++ b/llvm/test/CodeGen/M68k/CConv/c-call.ll
@@ -14,7 +14,7 @@ define i32 @test1() nounwind {
; CHECK-NEXT: move.l #2, (4,%sp)
; CHECK-NEXT: move.l #1, (%sp)
; CHECK-NEXT: jsr (test1_callee at PLT,%pc)
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
entry:
@@ -34,7 +34,7 @@ define i16 @test2() nounwind {
; CHECK-NEXT: move.l #2, (4,%sp)
; CHECK-NEXT: move.l #1, (%sp)
; CHECK-NEXT: jsr (test2_callee at PLT,%pc)
-; CHECK-NEXT: move.w #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
entry:
@@ -54,7 +54,7 @@ define i8 @test3() nounwind {
; CHECK-NEXT: move.l #2, (4,%sp)
; CHECK-NEXT: move.l #1, (%sp)
; CHECK-NEXT: jsr (test3_callee at PLT,%pc)
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
entry:
diff --git a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
index 4b0f8ed254a5e6..8d40ebd5228fc9 100644
--- a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
+++ b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
@@ -11,12 +11,12 @@ define i32 @foo1() nounwind uwtable {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -8
; CHECK-NEXT: move.l #5, (%sp)
-; CHECK-NEXT: move.l #1, %d0
-; CHECK-NEXT: move.l #2, %d1
+; CHECK-NEXT: moveq #1, %d0
+; CHECK-NEXT: moveq #2, %d1
; CHECK-NEXT: move.l #3, %a0
; CHECK-NEXT: move.l #4, %a1
; CHECK-NEXT: jsr (bar1 at PLT,%pc)
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
entry:
@@ -34,11 +34,11 @@ define i32 @foo2() nounwind uwtable {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -16
; CHECK-NEXT: lea (8,%sp), %a0
-; CHECK-NEXT: move.l #2, %d0
+; CHECK-NEXT: moveq #2, %d0
; CHECK-NEXT: lea (4,%sp), %a1
-; CHECK-NEXT: move.l #4, %d1
+; CHECK-NEXT: moveq #4, %d1
; CHECK-NEXT: jsr (bar2 at PLT,%pc)
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
index ce8f2d0a6ba760..3d398afe7dc487 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
@@ -71,7 +71,7 @@ define i32 @my_access_global_store_d() #0 {
; CHECK-NEXT: ; %bb.0: ; %entry
; CHECK-NEXT: move.l (d at GOTPCREL,%pc), %a0
; CHECK-NEXT: move.l #2, (%a0)
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
entry:
store i32 2, ptr @d, align 4
@@ -105,7 +105,7 @@ define linkonce_odr i32 @bar() comdat {
; CHECK-LABEL: bar:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
entry:
ret i32 0
diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
index 668f8a96ac6f95..030f72bb3753f8 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
@@ -69,7 +69,7 @@ define i32 @my_access_global_store_d() #0 {
; CHECK-NEXT: ; %bb.0: ; %entry
; CHECK-NEXT: move.l (d at GOTPCREL,%pc), %a0
; CHECK-NEXT: move.l #2, (%a0)
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
entry:
store i32 2, ptr @d, align 4
@@ -103,7 +103,7 @@ define linkonce_odr i32 @bar() comdat {
; CHECK-LABEL: bar:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
entry:
ret i32 0
diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll
index 634c08760a4e06..d3a8bbb0b0c8fb 100644
--- a/llvm/test/CodeGen/M68k/Control/cmp.ll
+++ b/llvm/test/CodeGen/M68k/Control/cmp.ll
@@ -8,10 +8,10 @@ define i32 @test1(ptr %y) nounwind {
; CHECK-NEXT: cmpi.l #0, (%a0)
; CHECK-NEXT: beq .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %cond_false
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB0_2: ; %cond_true
-; CHECK-NEXT: move.l #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: rts
%tmp = load i32, ptr %y ; <i32> [#uses=1]
%tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; <i1> [#uses=1]
@@ -33,10 +33,10 @@ define i32 @test2(ptr %y) nounwind {
; CHECK-NEXT: cmpi.l #0, %d0
; CHECK-NEXT: beq .LBB1_2
; CHECK-NEXT: ; %bb.1: ; %cond_false
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB1_2: ; %cond_true
-; CHECK-NEXT: move.l #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: rts
%tmp = load i32, ptr %y ; <i32> [#uses=1]
%tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
@@ -59,10 +59,10 @@ define i8 @test2b(ptr %y) nounwind {
; CHECK-NEXT: cmpi.b #0, %d0
; CHECK-NEXT: beq .LBB2_2
; CHECK-NEXT: ; %bb.1: ; %cond_false
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB2_2: ; %cond_true
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: rts
%tmp = load i8, ptr %y ; <i8> [#uses=1]
%tmp1 = shl i8 %tmp, 3 ; <i8> [#uses=1]
@@ -84,7 +84,7 @@ define i64 @test3(i64 %x) nounwind {
; CHECK-NEXT: seq %d0
; CHECK-NEXT: move.l %d0, %d1
; CHECK-NEXT: and.l #255, %d1
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
%t = icmp eq i64 %x, 0
%r = zext i1 %t to i64
@@ -97,7 +97,7 @@ define i64 @test4(i64 %x) nounwind {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l (8,%sp), %d1
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: move.l (12,%sp), %d2
; CHECK-NEXT: sub.l #1, %d2
; CHECK-NEXT: subx.l %d0, %d1
@@ -119,11 +119,11 @@ define i32 @test6() nounwind align 2 {
; CHECK-NEXT: or.l (8,%sp), %d0
; CHECK-NEXT: beq .LBB5_1
; CHECK-NEXT: ; %bb.2: ; %F
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB5_1: ; %T
-; CHECK-NEXT: move.l #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
%A = alloca {i64, i64}, align 8
@@ -229,7 +229,7 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
; CHECK-LABEL: test15:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #16, %d0
+; CHECK-NEXT: moveq #16, %d0
; CHECK-NEXT: move.l (4,%sp), %d1
; CHECK-NEXT: lsr.l %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
@@ -252,7 +252,7 @@ define i8 @test16(i16 signext %L) {
; CHECK-LABEL: test16:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.w #15, %d1
+; CHECK-NEXT: moveq #15, %d1
; CHECK-NEXT: move.w (6,%sp), %d0
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: eori.b #1, %d0
@@ -268,7 +268,7 @@ define i8 @test18(i64 %L) {
; CHECK-LABEL: test18:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #31, %d1
+; CHECK-NEXT: moveq #31, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsr.l %d1, %d0
; CHECK-NEXT: eori.b #1, %d0
diff --git a/llvm/test/CodeGen/M68k/Control/long-setcc.ll b/llvm/test/CodeGen/M68k/Control/long-setcc.ll
index b089af5f2ae874..45a617599c1eb8 100644
--- a/llvm/test/CodeGen/M68k/Control/long-setcc.ll
+++ b/llvm/test/CodeGen/M68k/Control/long-setcc.ll
@@ -4,7 +4,7 @@
define i1 @t1(i64 %x) nounwind {
; CHECK-LABEL: t1:
; CHECK: ; %bb.0:
-; CHECK-NEXT: move.l #31, %d1
+; CHECK-NEXT: moveq #31, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsr.l %d1, %d0
; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
@@ -26,7 +26,7 @@ define i1 @t2(i64 %x) nounwind {
define i1 @t3(i32 %x) nounwind {
; CHECK-LABEL: t3:
; CHECK: ; %bb.0:
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
%tmp = icmp ugt i32 %x, -1
ret i1 %tmp
diff --git a/llvm/test/CodeGen/M68k/Control/setcc.ll b/llvm/test/CodeGen/M68k/Control/setcc.ll
index 63856e278c9ee5..9e03f9b90842ac 100644
--- a/llvm/test/CodeGen/M68k/Control/setcc.ll
+++ b/llvm/test/CodeGen/M68k/Control/setcc.ll
@@ -40,7 +40,7 @@ define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
-; CHECK-NEXT: move.l #0, %d2
+; CHECK-NEXT: moveq #0, %d2
; CHECK-NEXT: sub.l #18, %d1
; CHECK-NEXT: subx.l %d2, %d0
; CHECK-NEXT: scs %d0
@@ -61,7 +61,7 @@ define i8 @t5(i32 %a) {
; CHECK-LABEL: t5:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #31, %d1
+; CHECK-NEXT: moveq #31, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsr.l %d1, %d0
; CHECK-NEXT: eori.b #1, %d0
@@ -86,7 +86,7 @@ define zeroext i1 @t6(i32 %a) {
; CHECK-LABEL: t6:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #31, %d0
+; CHECK-NEXT: moveq #31, %d0
; CHECK-NEXT: move.l (4,%sp), %d1
; CHECK-NEXT: lsr.l %d0, %d1
; CHECK-NEXT: eori.b #1, %d1
diff --git a/llvm/test/CodeGen/M68k/PR57660.ll b/llvm/test/CodeGen/M68k/PR57660.ll
index 184c30a33d7919..bad949b08cafac 100644
--- a/llvm/test/CodeGen/M68k/PR57660.ll
+++ b/llvm/test/CodeGen/M68k/PR57660.ll
@@ -7,7 +7,7 @@ define dso_local void @foo1() {
; CHECK-NEXT: ; %bb.0: ; %entry
; CHECK-NEXT: suba.l #2, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -6
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
; CHECK-NEXT: .LBB0_1: ; %do.body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/M68k/gcc_except_table.ll b/llvm/test/CodeGen/M68k/gcc_except_table.ll
index a7d2a6662724ed..fe0ed7861dfee8 100644
--- a/llvm/test/CodeGen/M68k/gcc_except_table.ll
+++ b/llvm/test/CodeGen/M68k/gcc_except_table.ll
@@ -19,7 +19,7 @@ define i32 @foo() uwtable ssp personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: jsr _Z1fv at PLT
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: ; %bb.1: ; %try.cont
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB0_2: ; %lpad
diff --git a/llvm/test/CodeGen/M68k/link-unlnk.ll b/llvm/test/CodeGen/M68k/link-unlnk.ll
index dfdd80e66ade78..fe39a9a13494a1 100644
--- a/llvm/test/CodeGen/M68k/link-unlnk.ll
+++ b/llvm/test/CodeGen/M68k/link-unlnk.ll
@@ -105,7 +105,7 @@ define i32 @test_gep() {
; FP-NEXT: .cfi_def_cfa_register %a6
; FP-NEXT: move.l #21, (-4,%a6)
; FP-NEXT: move.l #12, (-256,%a6)
-; FP-NEXT: move.l #0, %d0
+; FP-NEXT: moveq #0, %d0
; FP-NEXT: unlk %a6
; FP-NEXT: rts
;
@@ -116,7 +116,7 @@ define i32 @test_gep() {
; NO-FP-NEXT: .cfi_def_cfa_offset -260
; NO-FP-NEXT: move.l #21, (252,%sp)
; NO-FP-NEXT: move.l #12, (0,%sp)
-; NO-FP-NEXT: move.l #0, %d0
+; NO-FP-NEXT: moveq #0, %d0
; NO-FP-NEXT: adda.l #256, %sp
; NO-FP-NEXT: rts
entry:
diff --git a/llvm/test/MC/Disassembler/M68k/data.txt b/llvm/test/MC/Disassembler/M68k/data.txt
index 8e2fb3f1356086..3951ea677f11f7 100644
--- a/llvm/test/MC/Disassembler/M68k/data.txt
+++ b/llvm/test/MC/Disassembler/M68k/data.txt
@@ -36,6 +36,12 @@
# CHECK: move.l (64,%sp,%a0), %d0
0x20 0x37 0x88 0x40
+# CHECK: move.b #234, %d2
+0x14 0x3c 0x00 0xea
+
+# CHECK: moveq #100, %d2
+0x74 0x64
+
# CHECK: move.l $f0000000, %a5
0x2a 0x79 0xf0 0x00 0x00 0x00
diff --git a/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s b/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s
index 091367a6825668..2081924d7b17d2 100644
--- a/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s
+++ b/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s
@@ -9,3 +9,6 @@ move.l #42, %a1
; CHECK: move.l #-1, %a1
; CHECK-SAME: encoding: [0x22,0x7c,0xff,0xff,0xff,0xff]
move.l #-1, %a1
+; CHECK: moveq #-17, %d3
+; CHECK-SAME: encoding: [0x76,0xef]
+moveq #-17, %d3
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