[llvm] [TableGen] New tblgen Instruction bit to disable DAGISel pattern imports (PR #88382)

[via llvm-commits]

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/88382

>From f4e7c49aebeed2d253049d86943c36681c17f84c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 11 Apr 2024 01:15:36 -0400
Subject: [PATCH 1/2] [TableGen] New tblgen Instruction bit to disable DAGISel
 pattern imports

Added a new DAGISelShouldIgnore property to class Instruction in Target.td, similar to FastISelShouldIgnore. This allows one to avoid a record's DAGISel .td implementation and .inc generation.
---
 llvm/include/llvm/Target/Target.td                |  4 ++++
 llvm/utils/TableGen/Common/CodeGenInstruction.cpp |  1 +
 llvm/utils/TableGen/Common/CodeGenInstruction.h   |  1 +
 llvm/utils/TableGen/DAGISelEmitter.cpp            | 15 ++++++++++++++-
 4 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 1f7dc6922f13e4..61dc04595b62b9 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -777,6 +777,10 @@ class Instruction : InstructionEncoding {
   /// SelectionDAG can.
   bit FastISelShouldIgnore = false;
 
+  /// Should DAGISel ignore this instruction. In cases where lowering may
+  /// be done elsewhere or is unneeded, DAGISel may skip over them.
+  bit DAGISelShouldIgnore = false;
+
   /// HasPositionOrder: Indicate tablegen to sort the instructions by record
   /// ID, so that instruction that is defined earlier can be sorted earlier
   /// in the assembly matching table.
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index 18a4e7b0f18b23..a76efb76bfc319 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -465,6 +465,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
   isConvergent = R->getValueAsBit("isConvergent");
   hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
   FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
+  DAGISelShouldIgnore = R->getValueAsBit("DAGISelShouldIgnore");
   variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
   isAuthenticated = R->getValueAsBit("isAuthenticated");
 
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index b658259b4892ee..c36bfba245f66b 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -282,6 +282,7 @@ class CodeGenInstruction {
   bool isConvergent : 1;
   bool hasNoSchedulingInfo : 1;
   bool FastISelShouldIgnore : 1;
+  bool DAGISelShouldIgnore : 1;
   bool hasChain : 1;
   bool hasChain_Inferred : 1;
   bool variadicOpsAreDefs : 1;
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index b43a8e659dd9c5..4fbeafdc2355fb 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -165,8 +165,21 @@ void DAGISelEmitter::run(raw_ostream &OS) {
   // Add all the patterns to a temporary list so we can sort them.
   Records.startTimer("Sort patterns");
   std::vector<const PatternToMatch *> Patterns;
-  for (const PatternToMatch &PTM : CGP.ptms())
+  for (const PatternToMatch &PTM : CGP.ptms()) {
+
+    // Disable import of patterns marked as ignore.
+    const TreePatternNode &Dst = PTM.getDstPattern();
+    if (!Dst.isLeaf()) {
+      const Record *Op = Dst.getOperator();
+      const bool shouldIgnore =
+          Op->isSubClassOf("Instruction") &&
+          CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
+      if (shouldIgnore)
+        continue;
+    }
+
     Patterns.push_back(&PTM);
+  }
 
   // We want to process the matches in order of minimal cost.  Sort the patterns
   // so the least cost one is at the start.

>From ad38450e674b228eeb5735aa41c7c5c9331e559c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 12 Apr 2024 12:14:38 -0400
Subject: [PATCH 2/2] [TableGen] Add test for DAGISelShouldIgnore

This test ensures no .inc code is generated in the MatcherTable for the corresponding marked .td record.
---
 .../TableGen/DAGISelEmitter-shouldignore.td   | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 llvm/test/TableGen/DAGISelEmitter-shouldignore.td

diff --git a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
new file mode 100644
index 00000000000000..61dac212a716e0
--- /dev/null
+++ b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
@@ -0,0 +1,37 @@
+// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s -DIGNORE | FileCheck %s
+// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s --match-prefix=CHECK_LOOK | FileCheck --check-prefix=CHECK_LOOK %s
+
+include "llvm/Target/Target.td"
+def ISA : InstrInfo;
+def Tgt : Target { let InstructionSet = ISA; }
+def R0 : Register<"r0"> { let Namespace = "Tgt"; }
+def RC : RegisterClass<"Tgt", [i32], 32, (add R0)>;
+def Op : RegisterOperand<RC>;
+
+class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
+  let Namespace = "Tgt";
+  let OutOperandList = OOps;
+  let InOperandList = IOps;
+  let Pattern = Pat;
+}
+
+#ifdef IGNORE
+let DAGISelShouldIgnore = 1 in
+def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt), []>;
+// CHECK: static const unsigned char MatcherTable[] = {
+// CHECK-NEXT:  0
+// CHECK-NEXT: }; // Total Array size is 1 bytes
+#else
+def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt),
+           [(set Op:$rd, (add Op:$rs, Op:$rt))]>;
+// CHECK_LOOK:static const unsigned char MatcherTable[] = {
+// CHECK_LOOK-NEXT:/*     0*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+// CHECK_LOOK-NEXT:/*     3*/ OPC_RecordChild0, // #0 = $rs
+// CHECK_LOOK-NEXT:/*     4*/ OPC_RecordChild1, // #1 = $rt
+// CHECK_LOOK-NEXT:/*     5*/ OPC_MorphNodeTo1None, TARGET_VAL(Tgt::ADD),
+// CHECK_LOOK-NEXT:             MVT::i32, 2/*#Ops*/, 0, 1,
+// CHECK_LOOK-NEXT:// Src: (add:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt) - Complexity = {{[0-9]+}}
+// CHECK_LOOK-NEXT:// Dst: (ADD:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt)
+// CHECK_LOOK-NEXT: 0
+// CHECK_LOOK-NEXT:}; // Total Array size is 13 bytes
+#endif