[llvm] Base with add like constant offset (PR #88493)

[via llvm-commits]

https://github.com/fengfeng09 updated https://github.com/llvm/llvm-project/pull/88493

>From 9eb0bdf16cc3ddc9a320e51dea929a7f535af2b0 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 11:06:35 +0800
Subject: [PATCH 1/2] Precommit test for refine isBaseWithConstantOffset. NFC

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 .../AVR/base-with-add-like-constant-offset.ll | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll

diff --git a/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll b/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
new file mode 100644
index 00000000000000..ebb90a7c60c591
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=avr %s -start-before=avr-isel -o - | FileCheck %s
+
+define void @test(i16 %x, ptr addrspace(1) %o) {
+; CHECK-LABEL: test:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    ori r22, 10
+; CHECK-NEXT:    mov r30, r22
+; CHECK-NEXT:    mov r31, r23
+; CHECK-NEXT:    std Z+1, r25
+; CHECK-NEXT:    st Z, r24
+; CHECK-NEXT:    ret
+  %int = ptrtoint ptr addrspace(1) %o to i16
+  %or = or disjoint i16 %int, 10
+  %addr = inttoptr i16 %or to ptr addrspace(1)
+  store i16 %x, ptr addrspace(1) %addr
+  ret void
+}
+

>From f20ac0a617c410eae1297649e299f1244f1f6bb6 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 17:51:05 +0800
Subject: [PATCH 2/2] [SelectionDAG] Disjoint Or could be also constant offset.

If the addr base of a Load/Store Inst is an Or-disjoint with a constant,
it could be selected to an MI with constans offset if the target have.

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp        | 11 ++---------
 .../CodeGen/AVR/base-with-add-like-constant-offset.ll |  5 ++---
 2 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1dd0fa49a460f8..251d84e0b0a366 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5191,15 +5191,8 @@ bool SelectionDAG::isADDLike(SDValue Op) const {
 }
 
 bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
-  if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
-      !isa<ConstantSDNode>(Op.getOperand(1)))
-    return false;
-
-  if (Op.getOpcode() == ISD::OR &&
-      !MaskedValueIsZero(Op.getOperand(0), Op.getConstantOperandAPInt(1)))
-    return false;
-
-  return true;
+  return (Op.getOpcode() == ISD::ADD || isADDLike(Op)) &&
+         isa<ConstantSDNode>(Op.getOperand(1));
 }
 
 bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const {
diff --git a/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll b/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
index ebb90a7c60c591..278dc4893a68d4 100644
--- a/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
+++ b/llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll
@@ -4,11 +4,10 @@
 define void @test(i16 %x, ptr addrspace(1) %o) {
 ; CHECK-LABEL: test:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    ori r22, 10
 ; CHECK-NEXT:    mov r30, r22
 ; CHECK-NEXT:    mov r31, r23
-; CHECK-NEXT:    std Z+1, r25
-; CHECK-NEXT:    st Z, r24
+; CHECK-NEXT:    std Z+11, r25
+; CHECK-NEXT:    std Z+10, r24
 ; CHECK-NEXT:    ret
   %int = ptrtoint ptr addrspace(1) %o to i16
   %or = or disjoint i16 %int, 10