[llvm] [SelectionDAG] Propogate Disjoint flag. (PR #88370)

[via llvm-commits]

https://github.com/fengfeng09 updated https://github.com/llvm/llvm-project/pull/88370

>From 6a5f3d415429645aa2273ab72d089b105e84b551 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 00:29:12 +0800
Subject: [PATCH 1/2] Precommit test for propogate disjoint.NFC

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 .../X86/propogate-disjoint-in-shl-or.ll        | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll

diff --git a/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
new file mode 100644
index 00000000000000..2d79c0803dfbb3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64 %s -start-before=x86-isel -o - | FileCheck %s
+
+define void @add_shl_or_disjoint(i32 %x, ptr addrspace(1) %o) {
+; CHECK-LABEL: add_shl_or_disjoint:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shll $2, %edi
+; CHECK-NEXT:    orl $-1069531068, %edi # imm = 0xC0404044
+; CHECK-NEXT:    addl $1234567890, %edi # imm = 0x499602D2
+; CHECK-NEXT:    movl %edi, (%rsi)
+; CHECK-NEXT:    retq
+  %or = or disjoint i32 %x, 4027584529
+  %shl = shl i32 %or, 2
+  %add = add i32 %shl, 1234567890
+  store i32 %add, ptr addrspace(1) %o
+  ret void
+}
+

>From a1973f9cc06c754b0d482f11279988c8bc2475de Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 00:32:59 +0800
Subject: [PATCH 2/2] [SelectionDAG] Propogate Disjoint flag.

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp         | 2 ++
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp      | 2 ++
 llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll | 7 +++----
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8fe074666a3dc9..59ef66fba73164 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9530,6 +9530,8 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) {
   SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT);
   SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC);
   SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1);
+  // Propogate flags.
+  SelectionDAG::FlagInserter FlagsInserter(DAG, LogicOp->getFlags());
   return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2);
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 409d66adfd67d1..dd5c3d741aa7dc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -544,6 +544,8 @@ bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
     if (!C.isSubsetOf(DemandedBits)) {
       EVT VT = Op.getValueType();
       SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT);
+      // Propogate flags.
+      SelectionDAG::FlagInserter FlagsInserter(TLO.DAG, Op->getFlags());
       SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
       return TLO.CombineTo(Op, NewOp);
     }
diff --git a/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
index 2d79c0803dfbb3..496c87c72fbcf2 100644
--- a/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
+++ b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
@@ -4,10 +4,9 @@
 define void @add_shl_or_disjoint(i32 %x, ptr addrspace(1) %o) {
 ; CHECK-LABEL: add_shl_or_disjoint:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    shll $2, %edi
-; CHECK-NEXT:    orl $-1069531068, %edi # imm = 0xC0404044
-; CHECK-NEXT:    addl $1234567890, %edi # imm = 0x499602D2
-; CHECK-NEXT:    movl %edi, (%rsi)
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    leal 165036822(,%rdi,4), %eax
+; CHECK-NEXT:    movl %eax, (%rsi)
 ; CHECK-NEXT:    retq
   %or = or disjoint i32 %x, 4027584529
   %shl = shl i32 %or, 2