[llvm] [RISCV] Don't use V0 directly in patterns (PR #88496)

[Matt Arsenault via llvm-commits]

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@@ -549,7 +549,7 @@ def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>;
 
 def VRM8NoV0 : VReg<VM8VTs, (sub VRM8, V0M8), 8>;
 
-def VMV0 : VReg<VMaskVTs, (add V0), 1>;
+def VMV0 : VReg<VMaskVTs, (add V0, V0, V0, V0, V0), 1>;
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arsenm wrote:

What's going on here? Are you trying to define a register class with a single physical register, repeated multiple times? 

https://github.com/llvm/llvm-project/pull/88496