[llvm] [DAG] computeKnownBits - add ISD::ABDU/ISD::ABDS handling #84905 (PR #88253)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 12 04:19:58 PDT 2024
https://github.com/SahilPatidar updated https://github.com/llvm/llvm-project/pull/88253
>From a2b87f904b27374d5a9f6e4570ca8867e7463d98 Mon Sep 17 00:00:00 2001
From: SahilPatidar <patidarsahil2001 at gmail.com>
Date: Sat, 30 Mar 2024 11:21:40 +0530
Subject: [PATCH 1/3] add ISD::ABDU/ISD::ABDS handling #84905
---
.../CodeGen/AArch64/arm64-neon-aba-abd.ll | 183 ++++++++++++++++++
1 file changed, 183 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
index a13eac9b0a5e65..0c8d74095d872a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
@@ -291,3 +291,186 @@ define <2 x double> @test_fabd_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
%abd = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %lhs, <2 x double> %rhs)
ret <2 x double> %abd
}
+
+define <8 x i16> @test_uabd_knownbits_vec8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_uabd_knownbits_vec8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.8h, #15
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: ret
+ %and1 = and <8 x i16> %lhs, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+ %and2 = and <8 x i16> %rhs, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+ %uabd = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %and1, <8 x i16> %and2)
+ %suff = shufflevector <8 x i16> %uabd, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ %res = and <8 x i16> %suff, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @knownbits_uabd_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_uabd_mask_and_shuffle_lshr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ushr v0.4s, v0.4s, #17
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 65535, i32 65535, i32 65535, i32 65535>
+ %2 = and <4 x i32> %a1, <i32 65535, i32 65535, i32 65535, i32 65535>
+ %3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %1, <4 x i32> %2)
+ %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ %5 = lshr <4 x i32> %4, <i32 17, i32 17, i32 17, i32 17>
+ ret <4 x i32> %5
+}
+
+define <4 x i32> @knownbits_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_mask_and_shuffle_lshr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.4s, #127, msl #8
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ushr v0.4s, v0.4s, #17
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+ %2 = and <4 x i32> %a1, <i32 32767, i32 32767, i32 32767, i32 32767>
+ %3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %1, <4 x i32> %2)
+ %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %5 = lshr <4 x i32> %4, <i32 17, i32 17, i32 17, i32 17>
+ ret <4 x i32> %5
+}
+
+define <4 x i32> @test_sabd_knownbits_vec4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_sabd_knownbits_vec4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI31_0
+; CHECK-NEXT: adrp x9, .LCPI31_1
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI31_0]
+; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI31_1]
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: movi v1.2d, #0x0000ff000000ff
+; CHECK-NEXT: mov v0.s[1], v0.s[0]
+; CHECK-NEXT: trn2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %and1 = and <4 x i32> %lhs, <i32 255, i32 -1, i32 -1, i32 255>
+ %and2 = and <4 x i32> %rhs, <i32 255, i32 255, i32 -1, i32 -1>
+ %abd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %and1, <4 x i32> %and2)
+ %s = shufflevector <4 x i32> %abd, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
+ %4 = and <4 x i32> %s, <i32 255, i32 255, i32 255, i32 255>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @knownbits_sabd_and_mask(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_sabd_and_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI32_0
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI32_0]
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: zip2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
+ %2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 255, i32 4085>
+ %3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %1, <4 x i32> %2)
+ %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
+ ret <4 x i32> %4
+}
+
+define <4 x i32> @knownbits_sabd_and_or_mask(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_sabd_and_or_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
+; CHECK-NEXT: adrp x8, .LCPI33_0
+; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: orr v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: zip2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
+ %2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
+ %3 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 255, i32 4085>
+ %4 = or <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>
+ %5 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %2, <4 x i32> %4)
+ %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
+ ret <4 x i32> %6
+}
+
+define <4 x i32> @knownbits_sabd_and_xor_mask(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_sabd_and_xor_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI34_0
+; CHECK-NEXT: movi v3.2d, #0x00ffff0000ffff
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI34_0]
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: eor v0.16b, v0.16b, v3.16b
+; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: zip2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
+ %2 = xor <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
+ %3 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 255, i32 4085>
+ %4 = xor <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>
+ %5 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %2, <4 x i32> %4)
+ %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
+ ret <4 x i32> %6
+}
+
+define <4 x i32> @knownbits_sabd_and_shl_mask(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_sabd_and_shl_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI35_0
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI35_0]
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: shl v0.4s, v0.4s, #17
+; CHECK-NEXT: shl v1.4s, v1.4s, #17
+; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: mov v0.s[1], v0.s[0]
+; CHECK-NEXT: trn2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
+ %2 = shl <4 x i32> %1, <i32 17, i32 17, i32 17, i32 17>
+ %3 = and <4 x i32> %a1, <i32 -65536, i32 -7, i32 -7, i32 -65536>
+ %4 = shl <4 x i32> %3, <i32 17, i32 17, i32 17, i32 17>
+ %5 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %2, <4 x i32> %4)
+ %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
+ ret <4 x i32> %6
+}
+
+define <4 x i32> @knownbits_sabd_and_mul_mask(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: knownbits_sabd_and_mul_mask:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI36_0
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI36_0]
+; CHECK-NEXT: and v3.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v2.16b, v1.16b, v2.16b
+; CHECK-NEXT: mul v0.4s, v0.4s, v3.4s
+; CHECK-NEXT: mul v1.4s, v1.4s, v2.4s
+; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: mov v0.s[1], v0.s[0]
+; CHECK-NEXT: trn2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
+ %2 = mul <4 x i32> %a0, %1
+ %3 = and <4 x i32> %a1, <i32 -65536, i32 -7, i32 -7, i32 -65536>
+ %4 = mul <4 x i32> %a1, %3
+ %5 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %2, <4 x i32> %4)
+ %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
+ ret <4 x i32> %6
+}
>From 0863104c1bbd792c3fca5c397c16f8b60799594c Mon Sep 17 00:00:00 2001
From: SahilPatidar <patidarsahil2001 at gmail.com>
Date: Thu, 11 Apr 2024 16:23:11 +0530
Subject: [PATCH 2/3] add and update tests for known bit
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +++++++
.../CodeGen/AArch64/arm64-neon-aba-abd.ll | 34 +++----------------
2 files changed, 16 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1dd0fa49a460f8..a3953c2f29ffeb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3397,6 +3397,18 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known = KnownBits::mulhs(Known, Known2);
break;
}
+ case ISD::ABDU: {
+ Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+ Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+ Known = KnownBits::abdu(Known, Known2);
+ break;
+ }
+ case ISD::ABDS: {
+ Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+ Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+ Known = KnownBits::abds(Known, Known2);
+ break;
+ }
case ISD::UMUL_LOHI: {
assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result");
Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
index 0c8d74095d872a..cc9732b83e10c2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
@@ -301,7 +301,6 @@ define <8 x i16> @test_uabd_knownbits_vec8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: rev64 v0.8h, v0.8h
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret
%and1 = and <8 x i16> %lhs, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%and2 = and <8 x i16> %rhs, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -314,12 +313,7 @@ define <8 x i16> @test_uabd_knownbits_vec8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
define <4 x i32> @knownbits_uabd_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: knownbits_uabd_mask_and_shuffle_lshr:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: rev64 v0.4s, v0.4s
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ushr v0.4s, v0.4s, #17
; CHECK-NEXT: ret
%1 = and <4 x i32> %a0, <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -333,11 +327,7 @@ define <4 x i32> @knownbits_uabd_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32>
define <4 x i32> @knownbits_mask_and_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: knownbits_mask_and_shuffle_lshr:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: ushr v0.4s, v0.4s, #17
+; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ret
%1 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
%2 = and <4 x i32> %a1, <i32 32767, i32 32767, i32 32767, i32 32767>
@@ -390,15 +380,7 @@ define <4 x i32> @knownbits_sabd_and_mask(<4 x i32> %a0, <4 x i32> %a1) {
define <4 x i32> @knownbits_sabd_and_or_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: knownbits_sabd_and_or_mask:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
-; CHECK-NEXT: adrp x8, .LCPI33_0
-; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: orr v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: zip2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
%2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -434,15 +416,7 @@ define <4 x i32> @knownbits_sabd_and_xor_mask(<4 x i32> %a0, <4 x i32> %a1) {
define <4 x i32> @knownbits_sabd_and_shl_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: knownbits_sabd_and_shl_mask:
; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI35_0
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI35_0]
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: shl v0.4s, v0.4s, #17
-; CHECK-NEXT: shl v1.4s, v1.4s, #17
-; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: mov v0.s[1], v0.s[0]
-; CHECK-NEXT: trn2 v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
%2 = shl <4 x i32> %1, <i32 17, i32 17, i32 17, i32 17>
>From dcd6ba19c4c05539a70ec18c98a5c9923015468a Mon Sep 17 00:00:00 2001
From: SahilPatidar <patidarsahil2001 at gmail.com>
Date: Fri, 12 Apr 2024 16:43:39 +0530
Subject: [PATCH 3/3] update failing test
---
llvm/test/CodeGen/AArch64/abd-combine.ll | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/abd-combine.ll b/llvm/test/CodeGen/AArch64/abd-combine.ll
index cc29a59288c7dd..e48680f4be98b6 100644
--- a/llvm/test/CodeGen/AArch64/abd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/abd-combine.ll
@@ -530,13 +530,11 @@ define <8 x i16> @abds_i_reassoc(<8 x i16> %src1) {
define <1 x i64> @recursive() {
; CHECK-LABEL: recursive:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff
-; CHECK-NEXT: movi v1.8b, #1
-; CHECK-NEXT: uabd v2.8b, v1.8b, v0.8b
-; CHECK-NEXT: uabdl v0.8h, v1.8b, v0.8b
-; CHECK-NEXT: dup v1.8b, v2.b[0]
-; CHECK-NEXT: saddlp v0.1d, v0.2s
-; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: movi v0.8b, #254
+; CHECK-NEXT: ushll v1.8h, v0.8b, #0
+; CHECK-NEXT: dup v0.8b, v0.b[0]
+; CHECK-NEXT: saddlp v1.1d, v1.2s
+; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%1 = tail call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> zeroinitializer, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
%2 = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
More information about the llvm-commits
mailing list