[llvm] f5b2d24 - [NVPTX] Move roundeven on bf16 into the sm_90 has it but sm_80 doesn't bucket
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 12 02:49:11 PDT 2024
Author: Benjamin Kramer
Date: 2024-04-12T11:47:53+02:00
New Revision: f5b2d24b59f168eaeed08b5f45bf0c8dfcc1c292
URL: https://github.com/llvm/llvm-project/commit/f5b2d24b59f168eaeed08b5f45bf0c8dfcc1c292
DIFF: https://github.com/llvm/llvm-project/commit/f5b2d24b59f168eaeed08b5f45bf0c8dfcc1c292.diff
LOG: [NVPTX] Move roundeven on bf16 into the sm_90 has it but sm_80 doesn't bucket
Added:
Modified:
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/test/CodeGen/NVPTX/bf16-instructions.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index e1cdbd6a4b4dc6..44b61a937d64e4 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -447,6 +447,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
case ISD::FFLOOR:
case ISD::FNEARBYINT:
case ISD::FRINT:
+ case ISD::FROUNDEVEN:
case ISD::FTRUNC:
IsOpSupported = STI.getSmVersion() >= 90 && STI.getPTXVersion() >= 78;
break;
diff --git a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
index 884860712632d7..4cbab8bf24166c 100644
--- a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
@@ -330,3 +330,15 @@ define bfloat @test_uitofp_i64(i64 %a) {
%r = uitofp i64 %a to bfloat
ret bfloat %r
}
+
+; CHECK-LABEL: test_roundeven(
+; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_roundeven_param_0];
+; SM80: cvt.rni.f32.f32 [[F:%f[0-9]+]]
+; SM80: cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[F]];
+; SM90: cvt.rni.bf16.bf16 [[R:%rs[0-9]+]], [[A]];
+; CHECK: st.param.b16 [func_retval0+0], [[R]];
+; CHECK: ret;
+define bfloat @test_roundeven(bfloat %a) {
+ %r = call bfloat @llvm.roundeven.bf16(bfloat %a)
+ ret bfloat %r
+}
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