[llvm] [AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub. (PR #88413)

[David Green via llvm-commits]

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@@ -17942,11 +17942,13 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
       } else
         continue;
 
-      if (!ISD::isBuildVectorAllZeros(Sub.getOperand(0).getNode()))
+      if (!ISD::isBuildVectorAllZeros(Sub.getOperand(0).getNode()) &&
+          !ISD::isConstantSplatVectorAllZeros(Sub.getOperand(0).getNode()))
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davemgreen wrote:

I believe isBuildVectorAllZeros is just a sub-set of isConstantSplatVectorAllZeros (it just calls isConstantSplatVectorAllZeros with BuildVectorOnly=true). So hopefully only the second is needed.

https://github.com/llvm/llvm-project/pull/88413