[llvm] [RISCV] Support uimm32 immediates in RISCVInstrInfo::movImm for RV32. (PR #88464)

[Craig Topper via llvm-commits]

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@@ -767,8 +767,15 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
                             bool DstIsDead) const {
   Register SrcReg = RISCV::X0;
 
-  if (!STI.is64Bit() && !isInt<32>(Val))
-    report_fatal_error("Should only materialize 32-bit constants for RV32");
+  // For RV32, allow a sign or unsigned 32 bit value.
+  if (!STI.is64Bit() && !isInt<32>(Val)) {
+    // If have a uimm32 it will still fit in a register so we can allow it.
+    if (!isUInt<32>(Val))
+      report_fatal_error("Should only materialize 32-bit constants for RV32");
+
+    // Sign extend for generateInstSeq.
+    Val = SignExtend64<32>(Val);
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topperc wrote:

It’s already zero extended that’s what makes it uimm32. We need to sign extend it because the integer materialization expects simm32 for rv32.

https://github.com/llvm/llvm-project/pull/88464