[llvm] bf1d7b8 - [RISCV] Give HWASAN_CHECK_MEMACCESS_SHORTGRANULES pseudo the same code size as PseudoCall.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-04-11T17:13:51-07:00
New Revision: bf1d7b8df287d69ee265b91be40dec37267b2d5c

URL: https://github.com/llvm/llvm-project/commit/bf1d7b8df287d69ee265b91be40dec37267b2d5c
DIFF: https://github.com/llvm/llvm-project/commit/bf1d7b8df287d69ee265b91be40dec37267b2d5c.diff

LOG: [RISCV] Give HWASAN_CHECK_MEMACCESS_SHORTGRANULES pseudo the same code size as PseudoCall.

This is converted to a PseudoCall in RISCVAsmPrinter.cpp so it should
have the same size of 8 bytes.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 2cfad7f7c06110..f9dadc6c0d4895 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1861,7 +1861,7 @@ def : Pat<(trap), (UNIMP)>;
 def : Pat<(debugtrap), (EBREAK)>;
 
 let Predicates = [IsRV64], Uses = [X5],
-    Defs = [X1, X6, X7, X28, X29, X30, X31] in
+    Defs = [X1, X6, X7, X28, X29, X30, X31], Size = 8 in
 def HWASAN_CHECK_MEMACCESS_SHORTGRANULES
   : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo),
            [(int_hwasan_check_memaccess_shortgranules (i64 X5), GPRJALR:$ptr,