[llvm] [PowerPC] Spill non-volatile registers required for traceback table (PR #71115)
Maryam Moghadas via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 11 16:18:56 PDT 2024
https://github.com/maryammo updated https://github.com/llvm/llvm-project/pull/71115
>From c403ba4cb6bfd42037a3d973b5c6ba3c35af2415 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas <maryammo at ca.ibm.com>
Date: Fri, 27 Oct 2023 16:29:30 -0400
Subject: [PATCH 1/4] [PowerPC] Spill non-volatile registers required for
traceback table
On AIX we need to spill all [rfv]N-[rfv]31 when a function
clobbers [rfv]N so that the traceback table contains accurate
information.
---
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 62 +
llvm/lib/Target/PowerPC/PPCFrameLowering.h | 1 +
llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll | 17 +-
.../CodeGen/PowerPC/aix-csr-vector-extabi.ll | 1206 +++++++++++++----
llvm/test/CodeGen/PowerPC/aix-csr-vector.ll | 205 ++-
llvm/test/CodeGen/PowerPC/aix-csr.ll | 810 +++++++++--
.../test/CodeGen/PowerPC/aix-spills-for-eh.ll | 300 ++++
llvm/test/CodeGen/PowerPC/aix32-crsave.mir | 34 +-
.../CodeGen/PowerPC/ppc-shrink-wrapping.ll | 36 +-
llvm/test/CodeGen/PowerPC/ppc64-crsave.mir | 137 +-
10 files changed, 2334 insertions(+), 474 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 245e78641ed654..dd80d7558f5c5a 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1974,6 +1974,8 @@ void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs,
RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
+ if (Subtarget.isAIXABI())
+ updateCalleeSaves(MF, SavedRegs);
const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
@@ -2733,6 +2735,66 @@ bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();
}
+static bool isGPR(MCPhysReg Reg) { return Reg >= PPC::R0 && Reg <= PPC::R31; }
+static bool isG8R(MCPhysReg Reg) { return Reg >= PPC::X0 && Reg <= PPC::X31; }
+static bool isFPR(MCPhysReg Reg) { return Reg >= PPC::F0 && Reg <= PPC::F31; }
+static bool isVR(MCPhysReg Reg) { return Reg >= PPC::V0 && Reg <= PPC::V31; }
+
+void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
+ BitVector &SavedRegs) const {
+ // The AIX ABI uses traceback tables for EH which require that if callee-saved
+ // register N is used, all registers N-31 must be saved/restored.
+ // NOTE: The check for AIX is not actually what is relevant. Traceback tables
+ // on Linux have the same requirements. It is just that AIX is the only ABI
+ // for which we actually use traceback tables. If another ABI needs to be
+ // supported that also uses them, we can add a check such as
+ // Subtarget.usesTraceBackTables().
+ assert(Subtarget.isAIXABI() && "function only called for AIX");
+
+ // If there are no callee saves then there is nothing to do.
+ if (SavedRegs.none())
+ return;
+
+ const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
+ const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
+ MCPhysReg LowestGPR = PPC::R31;
+ MCPhysReg LowestG8R = PPC::X31;
+ MCPhysReg LowestFPR = PPC::F31;
+ MCPhysReg LowestVR = PPC::V31;
+
+ // Traverse the CSR's twice so as not to rely on ascending ordering of
+ // registers in the array. The first pass finds the lowest numbered
+ // register and the second pass marks all higher numbered registers
+ // for spilling.
+ for (int i = 0; CSRegs[i]; i++) {
+ // Get the lowest numbered register for each class that actually needs
+ // to be saved.
+ MCPhysReg Cand = CSRegs[i];
+ if (!SavedRegs.test(Cand))
+ continue;
+ if (isGPR(Cand) && Cand < LowestGPR)
+ LowestGPR = Cand;
+ else if (isG8R(Cand) && Cand < LowestG8R)
+ LowestG8R = Cand;
+ else if (isFPR(Cand) && Cand < LowestFPR)
+ LowestFPR = Cand;
+ else if (isVR(Cand) && Cand < LowestVR)
+ LowestVR = Cand;
+ }
+
+ for (int i = 0; CSRegs[i]; i++) {
+ MCPhysReg Cand = CSRegs[i];
+ if (isGPR(Cand) && Cand > LowestGPR)
+ SavedRegs.set(Cand);
+ else if (isG8R(Cand) && Cand > LowestG8R)
+ SavedRegs.set(Cand);
+ else if (isFPR(Cand) && Cand > LowestFPR)
+ SavedRegs.set(Cand);
+ else if (isVR(Cand) && Cand > LowestVR)
+ SavedRegs.set(Cand);
+ }
+}
+
uint64_t PPCFrameLowering::getStackThreshold() const {
// On PPC64, we use `stux r1, r1, <scratch_reg>` to extend the stack;
// use `add r1, r1, <scratch_reg>` to release the stack frame.
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.h b/llvm/lib/Target/PowerPC/PPCFrameLowering.h
index e19087ce0e1869..d74c87428326ca 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.h
@@ -173,6 +173,7 @@ class PPCFrameLowering: public TargetFrameLowering {
/// function prologue/epilogue.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
+ void updateCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const;
uint64_t getStackThreshold() const override;
};
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
index 77f3abb4ba2156..77a41ae1023c12 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
@@ -20,7 +20,7 @@
@gS1 = external global %struct_S1, align 1
-define void @call_test_byval_mem1() {
+define void @call_test_byval_mem1() #0 {
entry:
%call = call zeroext i8 @test_byval_mem1(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, ptr byval(%struct_S1) align 1 @gS1)
ret void
@@ -43,7 +43,7 @@ entry:
; ASM64BIT: bl .test_byval_mem1
; ASM64BIT: addi 1, 1, 128
-define zeroext i8 @test_byval_mem1(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S1) align 1 %s) {
+define zeroext i8 @test_byval_mem1(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S1) align 1 %s) #0 {
entry:
%load = load i8, ptr %s, align 1
ret i8 %load
@@ -70,7 +70,7 @@ entry:
@gS256 = external global %struct_S256, align 1
-define void @call_test_byval_mem2() {
+define void @call_test_byval_mem2() #0 {
entry:
%call = call zeroext i8 @test_byval_mem2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, ptr byval(%struct_S256) align 1 @gS256)
ret void
@@ -144,7 +144,7 @@ entry:
; ASM64BIT: addi 1, 1, 368
-define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S256) align 1 %s) {
+define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S256) align 1 %s) #0 {
entry:
%gep = getelementptr inbounds %struct_S256, ptr %s, i32 0, i32 0, i32 255
%load = load i8, ptr %gep, align 1
@@ -171,7 +171,7 @@ entry:
@gS57 = external global %struct_S57, align 1
-define void @call_test_byval_mem3() {
+define void @call_test_byval_mem3() #0 {
entry:
call void @test_byval_mem3(i32 42, float 0x40091EB860000000, ptr byval(%struct_S57) align 1 @gS57)
ret void
@@ -235,7 +235,7 @@ entry:
; ASM64BIT: bl .test_byval_mem3
; ASM64BIT: addi 1, 1, 128
-define void @test_byval_mem3(i32, float, ptr byval(%struct_S57) align 1 %s) {
+define void @test_byval_mem3(i32, float, ptr byval(%struct_S57) align 1 %s) #0 {
entry:
ret void
}
@@ -287,7 +287,7 @@ entry:
@gS31 = external global %struct_S31, align 1
-define void @call_test_byval_mem4() {
+define void @call_test_byval_mem4() #0 {
entry:
call void @test_byval_mem4(i32 42, ptr byval(%struct_S31) align 1 @gS31, ptr byval(%struct_S256) align 1 @gS256)
ret void
@@ -387,7 +387,7 @@ entry:
; ASM64BIT: bl .test_byval_mem4
; ASM64BIT: addi 1, 1, 352
-define void @test_byval_mem4(i32, ptr byval(%struct_S31) align 1, ptr byval(%struct_S256) align 1 %s) {
+define void @test_byval_mem4(i32, ptr byval(%struct_S31) align 1, ptr byval(%struct_S256) align 1 %s) #0 {
entry:
ret void
}
@@ -441,3 +441,4 @@ entry:
; 64BIT-DAG: STD %6, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8
; 64BIT-DAG: STD %7, 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
index 67397e4adf4e79..24311d38daa64e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
@@ -15,7 +15,7 @@
; RUN: FileCheck --check-prefix=ASM64 %s
-define dso_local void @vec_regs() {
+define dso_local void @vec_regs() #0 {
entry:
call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
ret void
@@ -23,94 +23,259 @@ entry:
; MIR32: name: vec_regs
-; MIR32-LABEL: fixedStack:
-; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-LABEL: fixedStack:
+; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -32, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -48, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -64, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -80, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -112, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -128, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -144, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 9, type: spill-slot, offset: -160, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 10, type: spill-slot, offset: -176, size: 16, alignment: 16,
+; MIR32-NEXT: stack-id: default, callee-saved-register: '$v21', callee-saved-restored: true,
+; MIR32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 11, type: spill-slot, offset: -192, size: 16, alignment: 16,
+; MIR32-NEXT: stack-id: default, callee-saved-register: '$v20', callee-saved-restored: true,
+; MIR32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR32-NEXT: stack:
-; MIR32: liveins: $v20, $v26, $v31
+; MIR32: liveins: $v20, $v21, $v22, $v23, $v24, $v25, $v26, $v27, $v28, $v29, $v30, $v31
-; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
-; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
-; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
+; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.11)
+; MIR32-DAG: STXVD2X killed $v21, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.10)
+; MIR32-DAG: STXVD2X killed $v22, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.9)
+; MIR32-DAG: STXVD2X killed $v23, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.8)
+; MIR32-DAG: STXVD2X killed $v24, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.7)
+; MIR32-DAG: STXVD2X killed $v25, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.6)
+; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.5)
+; MIR32-DAG: STXVD2X killed $v27, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.4)
+; MIR32-DAG: STXVD2X killed $v28, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.3)
+; MIR32-DAG: STXVD2X killed $v29, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
+; MIR32-DAG: STXVD2X killed $v30, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
; MIR32: INLINEASM
-; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
-; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.0)
+; MIR32-DAG: $v30 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
+; MIR32-DAG: $v29 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
+; MIR32-DAG: $v28 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.3)
+; MIR32-DAG: $v27 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.4)
+; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.5)
+; MIR32-DAG: $v25 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.6)
+; MIR32-DAG: $v24 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.7)
+; MIR32-DAG: $v23 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.8)
+; MIR32-DAG: $v22 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.9)
+; MIR32-DAG: $v21 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.10)
+; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.11)
; MIR32: BLR implicit $lr, implicit $rm
; MIR64: name: vec_regs
; MIR64-LABEL: fixedStack:
-; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 1, type: spill-slot, offset: -32, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 2, type: spill-slot, offset: -48, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 3, type: spill-slot, offset: -64, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 4, type: spill-slot, offset: -80, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 5, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 6, type: spill-slot, offset: -112, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 7, type: spill-slot, offset: -128, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 8, type: spill-slot, offset: -144, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 9, type: spill-slot, offset: -160, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 10, type: spill-slot, offset: -176, size: 16, alignment: 16,
+; MIR64-DAG: stack-id: default, callee-saved-register: '$v21', callee-saved-restored: true,
+; MIR64-DAG: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 11, type: spill-slot, offset: -192, size: 16, alignment: 16,
+; MIR64-DAG: stack-id: default, callee-saved-register: '$v20', callee-saved-restored: true,
+; MIR64-DAG: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR64-NEXT: stack:
-; MIR64: liveins: $v20, $v26, $v31
+; MIR64: liveins: $v20, $v21, $v22, $v23, $v24, $v25, $v26, $v27, $v28, $v29, $v30, $v31
-; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
-; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
-; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
+; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.11)
+; MIR64-DAG: STXVD2X killed $v21, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.10)
+; MIR64-DAG: STXVD2X killed $v22, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.9)
+; MIR64-DAG: STXVD2X killed $v23, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.8)
+; MIR64-DAG: STXVD2X killed $v24, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.7)
+; MIR64-DAG: STXVD2X killed $v25, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.6)
+; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.5)
+; MIR64-DAG: STXVD2X killed $v27, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.4)
+; MIR64-DAG: STXVD2X killed $v28, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.3)
+; MIR64-DAG: STXVD2X killed $v29, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
+; MIR64-DAG: STXVD2X killed $v30, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
-; MIR64: INLINEASM
+; MIR64: INLINEASM
-; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
-; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
-; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.0)
-; MIR64: BLR8 implicit $lr8, implicit $rm
+; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.0)
+; MIR64-DAG: $v30 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
+; MIR64-DAG: $v29 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
+; MIR64-DAG: $v28 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.3)
+; MIR64-DAG: $v27 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.4)
+; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.5)
+; MIR64-DAG: $v25 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.6)
+; MIR64-DAG: $v24 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.7)
+; MIR64-DAG: $v23 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.8)
+; MIR64-DAG: $v22 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.9)
+; MIR64-DAG: $v21 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.10)
+; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.11)
+; MIR64: BLR8 implicit $lr8, implicit $rm
; ASM32-LABEL: .vec_regs:
-; ASM32: li {{[0-9]+}}, -192
-; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM32-DAG: li {{[0-9]+}}, -96
-; ASM32-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM32-DAG: li {{[0-9]+}}, -16
-; ASM32-DAG: stxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM32: #APP
-; ASM32-DAG: #NO_APP
-; ASM32-DAG: lxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM32-DAG: li {{[0-9]+}}, -96
-; ASM32-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM32-DAG: li {{[0-9]+}}, -192
-; ASM32-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM32: blr
+; ASM32-DAG: li [[FIXEDSTACK11:[0-9]+]], -192
+; ASM32-DAG: stxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK10:[0-9]+]], -176
+; ASM32-DAG: stxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK9:[0-9]+]], -160
+; ASM32-DAG: stxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK8:[0-9]+]], -144
+; ASM32-DAG: stxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK7:[0-9]+]], -128
+; ASM32-DAG: stxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK6:[0-9]+]], -112
+; ASM32-DAG: stxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK5:[0-9]+]], -96
+; ASM32-DAG: stxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK4:[0-9]+]], -80
+; ASM32-DAG: stxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK3:[0-9]+]], -64
+; ASM32-DAG: stxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK2:[0-9]+]], -48
+; ASM32-DAG: stxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK1:[0-9]+]], -32
+; ASM32-DAG: stxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK0:[0-9]+]], -16
+; ASM32-DAG: stxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Spill
+
+; ASM32: #APP
+; ASM32-NEXT: #NO_APP
+
+; ASM32-DAG: lxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK1:[0-9]+]], -32
+; ASM32-DAG: lxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK2:[0-9]+]], -48
+; ASM32-DAG: lxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK3:[0-9]+]], -64
+; ASM32-DAG: lxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK4:[0-9]+]], -80
+; ASM32-DAG: lxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK5:[0-9]+]], -96
+; ASM32-DAG: lxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK6:[0-9]+]], -112
+; ASM32-DAG: lxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK7:[0-9]+]], -128
+; ASM32-DAG: lxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK8:[0-9]+]], -144
+; ASM32-DAG: lxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK9:[0-9]+]], -160
+; ASM32-DAG: lxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK10:[0-9]+]], -176
+; ASM32-DAG: lxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK11:[0-9]+]], -192
+; ASM32-DAG: lxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Reload
+; ASM32: blr
; ASM64-LABEL: .vec_regs:
-; ASM64-DAG: li {{[0-9]+}}, -192
-; ASM64-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM64-DAG: li {{[0-9]+}}, -96
-; ASM64-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM64-DAG: li {{[0-9]+}}, -16
-; ASM64-DAG: stxvd2x {{[0-9]+}}, 1, {{[0-9]+}} # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK11:[0-9]+]], -192
+; ASM64-DAG: stxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK10:[0-9]+]], -176
+; ASM64-DAG: stxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK9:[0-9]+]], -160
+; ASM64-DAG: stxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK8:[0-9]+]], -144
+; ASM64-DAG: stxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK7:[0-9]+]], -128
+; ASM64-DAG: stxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK6:[0-9]+]], -112
+; ASM64-DAG: stxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK5:[0-9]+]], -96
+; ASM64-DAG: stxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK4:[0-9]+]], -80
+; ASM64-DAG: stxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK3:[0-9]+]], -64
+; ASM64-DAG: stxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK2:[0-9]+]], -48
+; ASM64-DAG: stxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK1:[0-9]+]], -32
+; ASM64-DAG: stxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK0:[0-9]+]], -16
+; ASM64-DAG: stxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Spill
+
; ASM64-DAG: #APP
; ASM64-DAG: #NO_APP
-; ASM64-DAG: lxvd2x {{[0-9]+}}, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM64-DAG: li {{[0-9]+}}, -96
-; ASM64-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM64-DAG: li {{[0-9]+}}, -192
-; ASM64-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM64-DAG: blr
-
-define dso_local void @fprs_gprs_vecregs() {
+
+; ASM64-DAG: lxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK1:[0-9]+]], -32
+; ASM64-DAG: lxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK2:[0-9]+]], -48
+; ASM64-DAG: lxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK3:[0-9]+]], -64
+; ASM64-DAG: lxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK4:[0-9]+]], -80
+; ASM64-DAG: lxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK5:[0-9]+]], -96
+; ASM64-DAG: lxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK6:[0-9]+]], -112
+; ASM64-DAG: lxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK7:[0-9]+]], -128
+; ASM64-DAG: lxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK8:[0-9]+]], -144
+; ASM64-DAG: lxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK9:[0-9]+]], -160
+; ASM64-DAG: lxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK10:[0-9]+]], -176
+; ASM64-DAG: lxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK11:[0-9]+]], -192
+; ASM64-DAG: lxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Reload
+
+; ASM64: blr
+
+define dso_local void @fprs_gprs_vecregs() #0 {
call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
ret void
}
@@ -118,191 +283,768 @@ define dso_local void @fprs_gprs_vecregs() {
; MIR32: name: fprs_gprs_vecregs
; MIR32-LABEL: fixedStack:
-; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -240, size: 16, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -416, size: 16, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -240, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -256, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -272, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -288, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -336, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -352, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -368, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 9, type: spill-slot, offset: -384, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$v22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 10, type: spill-slot, offset: -400, size: 16, alignment: 16,
+; MIR32-NEXT: stack-id: default, callee-saved-register: '$v21', callee-saved-restored: true,
+; MIR32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 11, type: spill-slot, offset: -416, size: 16, alignment: 16,
+; MIR32-NEXT: stack-id: default, callee-saved-register: '$v20', callee-saved-restored: true,
+; MIR32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 12, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 13, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 14, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 15, type: spill-slot, offset: -32, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 16, type: spill-slot, offset: -40, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 17, type: spill-slot, offset: -48, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 18, type: spill-slot, offset: -56, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 19, type: spill-slot, offset: -64, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 20, type: spill-slot, offset: -72, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 21, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 22, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 23, type: spill-slot, offset: -96, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 24, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 25, type: spill-slot, offset: -112, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f18', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 26, type: spill-slot, offset: -120, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f17', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 27, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f16', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 28, type: spill-slot, offset: -136, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f15', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 29, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 30, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 31, type: spill-slot, offset: -152, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 32, type: spill-slot, offset: -156, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 33, type: spill-slot, offset: -160, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 34, type: spill-slot, offset: -164, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 35, type: spill-slot, offset: -168, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 36, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 37, type: spill-slot, offset: -176, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 38, type: spill-slot, offset: -180, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 39, type: spill-slot, offset: -184, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 40, type: spill-slot, offset: -188, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 41, type: spill-slot, offset: -192, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 42, type: spill-slot, offset: -196, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r19', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 43, type: spill-slot, offset: -200, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r18', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 44, type: spill-slot, offset: -204, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r17', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 45, type: spill-slot, offset: -208, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r16', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 46, type: spill-slot, offset: -212, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r15', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 47, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
; MIR32-NEXT: stack:
-; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31, $v20, $v26, $v31
-
-; MIR32-DAG: STW killed $r14, 232, $r1 :: (store (s32) into %fixed-stack.8, align 8)
-; MIR32-DAG: STW killed $r25, 276, $r1 :: (store (s32) into %fixed-stack.7)
-; MIR32-DAG: STW killed $r31, 300, $r1 :: (store (s32) into %fixed-stack.6)
-; MIR32-DAG: STFD killed $f14, 304, $r1 :: (store (s64) into %fixed-stack.5, align 16)
-; MIR32-DAG: STFD killed $f21, 360, $r1 :: (store (s64) into %fixed-stack.4)
-; MIR32-DAG: STFD killed $f31, 440, $r1 :: (store (s64) into %fixed-stack.3)
-; MIR32-DAG: $r{{[0-9]+}} = LI 32
-; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
-; MIR32-DAG: $r{{[0-9]+}} = LI 128
-; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
-; MIR32-DAG: $r{{[0-9]+}} = LI 208
+; MIR32: liveins: $r14, $r15, $r16, $r17, $r18, $r19, $r20, $r21, $r22, $r23, $r24, $r25, $r26, $r27, $r28, $r29, $r30, $r31, $f14, $f15, $f16, $f17, $f18, $f19, $f20, $f21, $f22, $f23, $f24, $f25, $f26, $f27, $f28, $f29, $f30, $f31, $v20, $v21, $v22, $v23, $v24, $v25, $v26, $v27, $v28, $v29, $v30, $v31
+
+; MIR32-DAG: STW killed $r14, 232, $r1 :: (store (s32) into %fixed-stack.47, align 8)
+; MIR32-DAG: STW killed $r15, 236, $r1 :: (store (s32) into %fixed-stack.46)
+; MIR32-DAG: STW killed $r16, 240, $r1 :: (store (s32) into %fixed-stack.45, align 16)
+; MIR32-DAG: STW killed $r17, 244, $r1 :: (store (s32) into %fixed-stack.44)
+; MIR32-DAG: STW killed $r18, 248, $r1 :: (store (s32) into %fixed-stack.43, align 8)
+; MIR32-DAG: STW killed $r19, 252, $r1 :: (store (s32) into %fixed-stack.42)
+; MIR32-DAG: STW killed $r20, 256, $r1 :: (store (s32) into %fixed-stack.41, align 16)
+; MIR32-DAG: STW killed $r21, 260, $r1 :: (store (s32) into %fixed-stack.40)
+; MIR32-DAG: STW killed $r22, 264, $r1 :: (store (s32) into %fixed-stack.39, align 8)
+; MIR32-DAG: STW killed $r23, 268, $r1 :: (store (s32) into %fixed-stack.38)
+; MIR32-DAG: STW killed $r24, 272, $r1 :: (store (s32) into %fixed-stack.37, align 16)
+; MIR32-DAG: STW killed $r25, 276, $r1 :: (store (s32) into %fixed-stack.36)
+; MIR32-DAG: STW killed $r26, 280, $r1 :: (store (s32) into %fixed-stack.35, align 8)
+; MIR32-DAG: STW killed $r27, 284, $r1 :: (store (s32) into %fixed-stack.34)
+; MIR32-DAG: STW killed $r28, 288, $r1 :: (store (s32) into %fixed-stack.33, align 16)
+; MIR32-DAG: STW killed $r29, 292, $r1 :: (store (s32) into %fixed-stack.32)
+; MIR32-DAG: STW killed $r30, 296, $r1 :: (store (s32) into %fixed-stack.31, align 8)
+; MIR32-DAG: STW killed $r31, 300, $r1 :: (store (s32) into %fixed-stack.30)
+; MIR32-DAG: STFD killed $f14, 304, $r1 :: (store (s64) into %fixed-stack.29, align 16)
+; MIR32-DAG: STFD killed $f15, 312, $r1 :: (store (s64) into %fixed-stack.28)
+; MIR32-DAG: STFD killed $f16, 320, $r1 :: (store (s64) into %fixed-stack.27, align 16)
+; MIR32-DAG: STFD killed $f17, 328, $r1 :: (store (s64) into %fixed-stack.26)
+; MIR32-DAG: STFD killed $f18, 336, $r1 :: (store (s64) into %fixed-stack.25, align 16)
+; MIR32-DAG: STFD killed $f19, 344, $r1 :: (store (s64) into %fixed-stack.24)
+; MIR32-DAG: STFD killed $f20, 352, $r1 :: (store (s64) into %fixed-stack.23, align 16)
+; MIR32-DAG: STFD killed $f21, 360, $r1 :: (store (s64) into %fixed-stack.22)
+; MIR32-DAG: STFD killed $f22, 368, $r1 :: (store (s64) into %fixed-stack.21, align 16)
+; MIR32-DAG: STFD killed $f23, 376, $r1 :: (store (s64) into %fixed-stack.20)
+; MIR32-DAG: STFD killed $f24, 384, $r1 :: (store (s64) into %fixed-stack.19, align 16)
+; MIR32-DAG: STFD killed $f25, 392, $r1 :: (store (s64) into %fixed-stack.18)
+; MIR32-DAG: STFD killed $f26, 400, $r1 :: (store (s64) into %fixed-stack.17, align 16)
+; MIR32-DAG: STFD killed $f27, 408, $r1 :: (store (s64) into %fixed-stack.16)
+; MIR32-DAG: STFD killed $f28, 416, $r1 :: (store (s64) into %fixed-stack.15, align 16)
+; MIR32-DAG: STFD killed $f29, 424, $r1 :: (store (s64) into %fixed-stack.14)
+; MIR32-DAG: STFD killed $f30, 432, $r1 :: (store (s64) into %fixed-stack.13, align 16)
+; MIR32-DAG: STFD killed $f31, 440, $r1 :: (store (s64) into %fixed-stack.12)
+; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.11)
+; MIR32-DAG: STXVD2X killed $v21, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.10)
+; MIR32-DAG: STXVD2X killed $v22, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.9)
+; MIR32-DAG: STXVD2X killed $v23, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.8)
+; MIR32-DAG: STXVD2X killed $v24, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.7)
+; MIR32-DAG: STXVD2X killed $v25, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.6)
+; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.5)
+; MIR32-DAG: STXVD2X killed $v27, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.4)
+; MIR32-DAG: STXVD2X killed $v28, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.3)
+; MIR32-DAG: STXVD2X killed $v29, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
+; MIR32-DAG: STXVD2X killed $v30, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
-; MIR32-DAG: $r1 = STWU $r1, -448, $r1
; MIR32: INLINEASM
-; MIR32-DAG: $r14 = LWZ 232, $r1 :: (load (s32) from %fixed-stack.8, align 8)
-; MIR32-DAG: $r25 = LWZ 276, $r1 :: (load (s32) from %fixed-stack.7)
-; MIR32-DAG: $r31 = LWZ 300, $r1 :: (load (s32) from %fixed-stack.6)
-; MIR32-DAG: $f14 = LFD 304, $r1 :: (load (s64) from %fixed-stack.5, align 16)
-; MIR32-DAG: $f21 = LFD 360, $r1 :: (load (s64) from %fixed-stack.4)
-; MIR32-DAG: $f31 = LFD 440, $r1 :: (load (s64) from %fixed-stack.3)
-; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
-; MIR32-DAG: $r{{[0-9]+}} = LI 32
-; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
-; MIR32-DAG: $r{{[0-9]+}} = LI 128
-; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load (s128) from %fixed-stack.0)
-; MIR32-DAG: $r{{[0-9]+}} = LI 208
-; MIR32-DAG: $r1 = ADDI $r1, 448
-; MIR32-DAG: BLR implicit $lr, implicit $rm
+; MIR32-DAG: $v31 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.0)
+; MIR32-DAG: $v30 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.1)
+; MIR32-DAG: $v29 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.2)
+; MIR32-DAG: $v28 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.3)
+; MIR32-DAG: $v27 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.4)
+; MIR32-DAG: $v26 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.5)
+; MIR32-DAG: $v25 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.6)
+; MIR32-DAG: $v24 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.7)
+; MIR32-DAG: $v23 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.8)
+; MIR32-DAG: $v22 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.9)
+; MIR32-DAG: $v21 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.10)
+; MIR32-DAG: $v20 = LXVD2X $r1, killed $r3 :: (load (s128) from %fixed-stack.11)
+; MIR32-DAG: $f31 = LFD 440, $r1 :: (load (s64) from %fixed-stack.12)
+; MIR32-DAG: $f30 = LFD 432, $r1 :: (load (s64) from %fixed-stack.13, align 16)
+; MIR32-DAG: $f29 = LFD 424, $r1 :: (load (s64) from %fixed-stack.14)
+; MIR32-DAG: $f28 = LFD 416, $r1 :: (load (s64) from %fixed-stack.15, align 16)
+; MIR32-DAG: $f27 = LFD 408, $r1 :: (load (s64) from %fixed-stack.16)
+; MIR32-DAG: $f26 = LFD 400, $r1 :: (load (s64) from %fixed-stack.17, align 16)
+; MIR32-DAG: $f25 = LFD 392, $r1 :: (load (s64) from %fixed-stack.18)
+; MIR32-DAG: $f24 = LFD 384, $r1 :: (load (s64) from %fixed-stack.19, align 16)
+; MIR32-DAG: $f23 = LFD 376, $r1 :: (load (s64) from %fixed-stack.20)
+; MIR32-DAG: $f22 = LFD 368, $r1 :: (load (s64) from %fixed-stack.21, align 16)
+; MIR32-DAG: $f21 = LFD 360, $r1 :: (load (s64) from %fixed-stack.22)
+; MIR32-DAG: $f20 = LFD 352, $r1 :: (load (s64) from %fixed-stack.23, align 16)
+; MIR32-DAG: $f19 = LFD 344, $r1 :: (load (s64) from %fixed-stack.24)
+; MIR32-DAG: $f18 = LFD 336, $r1 :: (load (s64) from %fixed-stack.25, align 16)
+; MIR32-DAG: $f17 = LFD 328, $r1 :: (load (s64) from %fixed-stack.26)
+; MIR32-DAG: $f16 = LFD 320, $r1 :: (load (s64) from %fixed-stack.27, align 16)
+; MIR32-DAG: $f15 = LFD 312, $r1 :: (load (s64) from %fixed-stack.28)
+; MIR32-DAG: $f14 = LFD 304, $r1 :: (load (s64) from %fixed-stack.29, align 16)
+; MIR32-DAG: $r31 = LWZ 300, $r1 :: (load (s32) from %fixed-stack.30)
+; MIR32-DAG: $r30 = LWZ 296, $r1 :: (load (s32) from %fixed-stack.31, align 8)
+; MIR32-DAG: $r29 = LWZ 292, $r1 :: (load (s32) from %fixed-stack.32)
+; MIR32-DAG: $r28 = LWZ 288, $r1 :: (load (s32) from %fixed-stack.33, align 16)
+; MIR32-DAG: $r27 = LWZ 284, $r1 :: (load (s32) from %fixed-stack.34)
+; MIR32-DAG: $r26 = LWZ 280, $r1 :: (load (s32) from %fixed-stack.35, align 8)
+; MIR32-DAG: $r25 = LWZ 276, $r1 :: (load (s32) from %fixed-stack.36)
+; MIR32-DAG: $r24 = LWZ 272, $r1 :: (load (s32) from %fixed-stack.37, align 16)
+; MIR32-DAG: $r23 = LWZ 268, $r1 :: (load (s32) from %fixed-stack.38)
+; MIR32-DAG: $r22 = LWZ 264, $r1 :: (load (s32) from %fixed-stack.39, align 8)
+; MIR32-DAG: $r21 = LWZ 260, $r1 :: (load (s32) from %fixed-stack.40)
+; MIR32-DAG: $r20 = LWZ 256, $r1 :: (load (s32) from %fixed-stack.41, align 16)
+; MIR32-DAG: $r19 = LWZ 252, $r1 :: (load (s32) from %fixed-stack.42)
+; MIR32-DAG: $r18 = LWZ 248, $r1 :: (load (s32) from %fixed-stack.43, align 8)
+; MIR32-DAG: $r17 = LWZ 244, $r1 :: (load (s32) from %fixed-stack.44)
+; MIR32-DAG: $r16 = LWZ 240, $r1 :: (load (s32) from %fixed-stack.45, align 16)
+; MIR32-DAG: $r15 = LWZ 236, $r1 :: (load (s32) from %fixed-stack.46)
+; MIR32-DAG: $r14 = LWZ 232, $r1 :: (load (s32) from %fixed-stack.47, align 8)
+; MIR32: $r1 = ADDI $r1, 448
+; MIR32-NEXT: BLR implicit $lr, implicit $rm
+
; MIR64: name: fprs_gprs_vecregs
; MIR64-LABEL: fixedStack:
-; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -384, size: 16, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -480, size: 16, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 6, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 7, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 8, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 0, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 1, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 2, type: spill-slot, offset: -336, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 3, type: spill-slot, offset: -352, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 4, type: spill-slot, offset: -368, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 5, type: spill-slot, offset: -384, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 6, type: spill-slot, offset: -400, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 7, type: spill-slot, offset: -416, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 8, type: spill-slot, offset: -432, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 9, type: spill-slot, offset: -448, size: 16, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$v22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 10, type: spill-slot, offset: -464, size: 16, alignment: 16,
+; MIR64-DAG: stack-id: default, callee-saved-register: '$v21', callee-saved-restored: true,
+; MIR64-DAG: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 11, type: spill-slot, offset: -480, size: 16, alignment: 16,
+; MIR64-DAG: stack-id: default, callee-saved-register: '$v20', callee-saved-restored: true,
+; MIR64-DAG: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 12, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 13, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 14, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 15, type: spill-slot, offset: -32, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 16, type: spill-slot, offset: -40, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 17, type: spill-slot, offset: -48, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 18, type: spill-slot, offset: -56, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 19, type: spill-slot, offset: -64, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 20, type: spill-slot, offset: -72, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 21, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 22, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 23, type: spill-slot, offset: -96, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 24, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 25, type: spill-slot, offset: -112, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f18', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 26, type: spill-slot, offset: -120, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f17', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 27, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f16', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 28, type: spill-slot, offset: -136, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f15', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 29, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 30, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 31, type: spill-slot, offset: -160, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 32, type: spill-slot, offset: -168, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 33, type: spill-slot, offset: -176, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 34, type: spill-slot, offset: -184, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 35, type: spill-slot, offset: -192, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 36, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 37, type: spill-slot, offset: -208, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 38, type: spill-slot, offset: -216, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 39, type: spill-slot, offset: -224, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 40, type: spill-slot, offset: -232, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 41, type: spill-slot, offset: -240, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 42, type: spill-slot, offset: -248, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x19', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 43, type: spill-slot, offset: -256, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x18', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 44, type: spill-slot, offset: -264, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x17', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 45, type: spill-slot, offset: -272, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x16', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 46, type: spill-slot, offset: -280, size: 8, alignment: 8, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x15', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
+; MIR64-DAG: - { id: 47, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
+; MIR64-DAG: callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-DAG: debug-info-expression: '', debug-info-location: '' }
; MIR64-NEXT: stack:
-; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31, $v20, $v26, $v31
-
-; MIR64-DAG: $x1 = STDU $x1, -544, $x1
-; MIR64-DAG: STD killed $x14, 256, $x1 :: (store (s64) into %fixed-stack.8, align 16)
-; MIR64-DAG: STD killed $x25, 344, $x1 :: (store (s64) into %fixed-stack.7)
-; MIR64-DAG: STD killed $x31, 392, $x1 :: (store (s64) into %fixed-stack.6)
-; MIR64-DAG: STFD killed $f14, 400, $x1 :: (store (s64) into %fixed-stack.5, align 16)
-; MIR64-DAG: STFD killed $f21, 456, $x1 :: (store (s64) into %fixed-stack.4)
-; MIR64-DAG: STFD killed $f31, 536, $x1 :: (store (s64) into %fixed-stack.3)
-; MIR64-DAG: $x{{[0-9]+}} = LI8 64
-; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
-; MIR64-DAG: $x{{[0-9]+}} = LI8 160
-; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
-; MIR64-DAG: $x{{[0-9]+}} = LI8 240
-; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
+; MIR64: liveins: $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31, $f14, $f15, $f16, $f17, $f18, $f19, $f20, $f21, $f22, $f23, $f24, $f25, $f26, $f27, $f28, $f29, $f30, $f31, $v20, $v21, $v22, $v23, $v24, $v25, $v26, $v27, $v28, $v29, $v30, $v31
+
+; MIR64: $x1 = STDU $x1, -544, $x1
+;MIR64-DAG: STD killed $x14, 256, $x1 :: (store (s64) into %fixed-stack.47, align 16)
+;MIR64-DAG: STD killed $x15, 264, $x1 :: (store (s64) into %fixed-stack.46)
+;MIR64-DAG: STD killed $x16, 272, $x1 :: (store (s64) into %fixed-stack.45, align 16)
+;MIR64-DAG: STD killed $x17, 280, $x1 :: (store (s64) into %fixed-stack.44)
+;MIR64-DAG: STD killed $x18, 288, $x1 :: (store (s64) into %fixed-stack.43, align 16)
+;MIR64-DAG: STD killed $x19, 296, $x1 :: (store (s64) into %fixed-stack.42)
+;MIR64-DAG: STD killed $x20, 304, $x1 :: (store (s64) into %fixed-stack.41, align 16)
+;MIR64-DAG: STD killed $x21, 312, $x1 :: (store (s64) into %fixed-stack.40)
+;MIR64-DAG: STD killed $x22, 320, $x1 :: (store (s64) into %fixed-stack.39, align 16)
+;MIR64-DAG: STD killed $x23, 328, $x1 :: (store (s64) into %fixed-stack.38)
+;MIR64-DAG: STD killed $x24, 336, $x1 :: (store (s64) into %fixed-stack.37, align 16)
+;MIR64-DAG: STD killed $x25, 344, $x1 :: (store (s64) into %fixed-stack.36)
+;MIR64-DAG: STD killed $x26, 352, $x1 :: (store (s64) into %fixed-stack.35, align 16)
+;MIR64-DAG: STD killed $x27, 360, $x1 :: (store (s64) into %fixed-stack.34)
+;MIR64-DAG: STD killed $x28, 368, $x1 :: (store (s64) into %fixed-stack.33, align 16)
+;MIR64-DAG: STD killed $x29, 376, $x1 :: (store (s64) into %fixed-stack.32)
+;MIR64-DAG: STD killed $x30, 384, $x1 :: (store (s64) into %fixed-stack.31, align 16)
+;MIR64-DAG: STD killed $x31, 392, $x1 :: (store (s64) into %fixed-stack.30)
+;MIR64-DAG: STFD killed $f14, 400, $x1 :: (store (s64) into %fixed-stack.29, align 16)
+;MIR64-DAG: STFD killed $f15, 408, $x1 :: (store (s64) into %fixed-stack.28)
+;MIR64-DAG: STFD killed $f16, 416, $x1 :: (store (s64) into %fixed-stack.27, align 16)
+;MIR64-DAG: STFD killed $f17, 424, $x1 :: (store (s64) into %fixed-stack.26)
+;MIR64-DAG: STFD killed $f18, 432, $x1 :: (store (s64) into %fixed-stack.25, align 16)
+;MIR64-DAG: STFD killed $f19, 440, $x1 :: (store (s64) into %fixed-stack.24)
+;MIR64-DAG: STFD killed $f20, 448, $x1 :: (store (s64) into %fixed-stack.23, align 16)
+;MIR64-DAG: STFD killed $f21, 456, $x1 :: (store (s64) into %fixed-stack.22)
+;MIR64-DAG: STFD killed $f22, 464, $x1 :: (store (s64) into %fixed-stack.21, align 16)
+;MIR64-DAG: STFD killed $f23, 472, $x1 :: (store (s64) into %fixed-stack.20)
+;MIR64-DAG: STFD killed $f24, 480, $x1 :: (store (s64) into %fixed-stack.19, align 16)
+;MIR64-DAG: STFD killed $f25, 488, $x1 :: (store (s64) into %fixed-stack.18)
+;MIR64-DAG: STFD killed $f26, 496, $x1 :: (store (s64) into %fixed-stack.17, align 16)
+;MIR64-DAG: STFD killed $f27, 504, $x1 :: (store (s64) into %fixed-stack.16)
+;MIR64-DAG: STFD killed $f28, 512, $x1 :: (store (s64) into %fixed-stack.15, align 16)
+;MIR64-DAG: STFD killed $f29, 520, $x1 :: (store (s64) into %fixed-stack.14)
+;MIR64-DAG: STFD killed $f30, 528, $x1 :: (store (s64) into %fixed-stack.13, align 16)
+;MIR64-DAG: STFD killed $f31, 536, $x1 :: (store (s64) into %fixed-stack.12)
+;MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.11)
+;MIR64-DAG: STXVD2X killed $v21, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.10)
+;MIR64-DAG: STXVD2X killed $v22, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.9)
+;MIR64-DAG: STXVD2X killed $v23, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.8)
+;MIR64-DAG: STXVD2X killed $v24, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.7)
+;MIR64-DAG: STXVD2X killed $v25, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.6)
+;MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.5)
+;MIR64-DAG: STXVD2X killed $v27, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.4)
+;MIR64-DAG: STXVD2X killed $v28, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.3)
+;MIR64-DAG: STXVD2X killed $v29, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
+;MIR64-DAG: STXVD2X killed $v30, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
+;MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
; MIR64: INLINEASM
-; MIR64-DAG: $x14 = LD 256, $x1 :: (load (s64) from %fixed-stack.8, align 16)
-; MIR64-DAG: $x25 = LD 344, $x1 :: (load (s64) from %fixed-stack.7)
-; MIR64-DAG: $x31 = LD 392, $x1 :: (load (s64) from %fixed-stack.6)
-; MIR64-DAG: $f14 = LFD 400, $x1 :: (load (s64) from %fixed-stack.5, align 16)
-; MIR64-DAG: $f21 = LFD 456, $x1 :: (load (s64) from %fixed-stack.4)
-; MIR64-DAG: $f31 = LFD 536, $x1 :: (load (s64) from %fixed-stack.3)
-; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
-; MIR64-DAG: $x{{[0-9]+}} = LI8 64
-; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
-; MIR64-DAG: $x{{[0-9]+}} = LI8 160
; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.0)
-; MIR64-DAG: $x{{[0-9]+}} = LI8 240
-; MIR64-DAG: $x1 = ADDI8 $x1, 544
-; MIR64-DAG: BLR8 implicit $lr8, implicit $rm
-
-; ASM32-LABEL: .fprs_gprs_vecregs:
-
-; ASM32: stwu 1, -448(1)
-; ASM32-DAG: li {{[0-9]+}}, 32
-; ASM32-DAG: stw 14, 232(1) # 4-byte Folded Spill
-; ASM32-DAG: stfd 14, 304(1) # 8-byte Folded Spill
-; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM32-DAG: li {{[0-9]+}}, 128
-; ASM32-DAG: stw 25, 276(1) # 4-byte Folded Spill
-; ASM32-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM32-DAG: li {{[0-9]+}}, 208
-; ASM32-DAG: stw 31, 300(1) # 4-byte Folded Spill
-; ASM32-DAG: stfd 21, 360(1) # 8-byte Folded Spill
-; ASM32-DAG: stfd 31, 440(1) # 8-byte Folded Spill
-; ASM32-DAG: stxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM32-DAG: #APP
-; ASM32-DAG: #NO_APP
-; ASM32-DAG: lxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM32-DAG: li {{[0-9]+}}, 128
-; ASM32-DAG: lfd 31, 440(1) # 8-byte Folded Reload
-; ASM32-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM32-DAG: li {{[0-9]+}}, 32
-; ASM32-DAG: lfd 21, 360(1) # 8-byte Folded Reload
-; ASM32-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM32-DAG: lfd 14, 304(1) # 8-byte Folded Reload
-; ASM32-DAG: lwz 31, 300(1) # 4-byte Folded Reload
-; ASM32-DAG: lwz 25, 276(1) # 4-byte Folded Reload
-; ASM32-DAG: lwz 14, 232(1) # 4-byte Folded Reload
-; ASM32-DAG: addi 1, 1, 448
-; ASM32: blr
+; MIR64-DAG: $v30 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.1)
+; MIR64-DAG: $v29 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.2)
+; MIR64-DAG: $v28 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.3)
+; MIR64-DAG: $v27 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.4)
+; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.5)
+; MIR64-DAG: $v25 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.6)
+; MIR64-DAG: $v24 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.7)
+; MIR64-DAG: $v23 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.8)
+; MIR64-DAG: $v22 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.9)
+; MIR64-DAG: $v21 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.10)
+; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load (s128) from %fixed-stack.11)
+; MIR64-DAG: $f31 = LFD 536, $x1 :: (load (s64) from %fixed-stack.12)
+; MIR64-DAG: $f30 = LFD 528, $x1 :: (load (s64) from %fixed-stack.13, align 16)
+; MIR64-DAG: $f29 = LFD 520, $x1 :: (load (s64) from %fixed-stack.14)
+; MIR64-DAG: $f28 = LFD 512, $x1 :: (load (s64) from %fixed-stack.15, align 16)
+; MIR64-DAG: $f27 = LFD 504, $x1 :: (load (s64) from %fixed-stack.16)
+; MIR64-DAG: $f26 = LFD 496, $x1 :: (load (s64) from %fixed-stack.17, align 16)
+; MIR64-DAG: $f25 = LFD 488, $x1 :: (load (s64) from %fixed-stack.18)
+; MIR64-DAG: $f24 = LFD 480, $x1 :: (load (s64) from %fixed-stack.19, align 16)
+; MIR64-DAG: $f23 = LFD 472, $x1 :: (load (s64) from %fixed-stack.20)
+; MIR64-DAG: $f22 = LFD 464, $x1 :: (load (s64) from %fixed-stack.21, align 16)
+; MIR64-DAG: $f21 = LFD 456, $x1 :: (load (s64) from %fixed-stack.22)
+; MIR64-DAG: $f20 = LFD 448, $x1 :: (load (s64) from %fixed-stack.23, align 16)
+; MIR64-DAG: $f19 = LFD 440, $x1 :: (load (s64) from %fixed-stack.24)
+; MIR64-DAG: $f18 = LFD 432, $x1 :: (load (s64) from %fixed-stack.25, align 16)
+; MIR64-DAG: $f17 = LFD 424, $x1 :: (load (s64) from %fixed-stack.26)
+; MIR64-DAG: $f16 = LFD 416, $x1 :: (load (s64) from %fixed-stack.27, align 16)
+; MIR64-DAG: $f15 = LFD 408, $x1 :: (load (s64) from %fixed-stack.28)
+; MIR64-DAG: $f14 = LFD 400, $x1 :: (load (s64) from %fixed-stack.29, align 16)
+; MIR64-DAG: $x31 = LD 392, $x1 :: (load (s64) from %fixed-stack.30)
+; MIR64-DAG: $x30 = LD 384, $x1 :: (load (s64) from %fixed-stack.31, align 16)
+; MIR64-DAG: $x29 = LD 376, $x1 :: (load (s64) from %fixed-stack.32)
+; MIR64-DAG: $x28 = LD 368, $x1 :: (load (s64) from %fixed-stack.33, align 16)
+; MIR64-DAG: $x27 = LD 360, $x1 :: (load (s64) from %fixed-stack.34)
+; MIR64-DAG: $x26 = LD 352, $x1 :: (load (s64) from %fixed-stack.35, align 16)
+; MIR64-DAG: $x25 = LD 344, $x1 :: (load (s64) from %fixed-stack.36)
+; MIR64-DAG: $x24 = LD 336, $x1 :: (load (s64) from %fixed-stack.37, align 16)
+; MIR64-DAG: $x23 = LD 328, $x1 :: (load (s64) from %fixed-stack.38)
+; MIR64-DAG: $x22 = LD 320, $x1 :: (load (s64) from %fixed-stack.39, align 16)
+; MIR64-DAG: $x21 = LD 312, $x1 :: (load (s64) from %fixed-stack.40)
+; MIR64-DAG: $x20 = LD 304, $x1 :: (load (s64) from %fixed-stack.41, align 16)
+; MIR64-DAG: $x19 = LD 296, $x1 :: (load (s64) from %fixed-stack.42)
+; MIR64-DAG: $x18 = LD 288, $x1 :: (load (s64) from %fixed-stack.43, align 16)
+; MIR64-DAG: $x17 = LD 280, $x1 :: (load (s64) from %fixed-stack.44)
+; MIR64-DAG: $x16 = LD 272, $x1 :: (load (s64) from %fixed-stack.45, align 16)
+; MIR64-DAG: $x15 = LD 264, $x1 :: (load (s64) from %fixed-stack.46)
+; MIR64-DAG: $x14 = LD 256, $x1 :: (load (s64) from %fixed-stack.47, align 16)
+; MIR64: $x1 = ADDI8 $x1, 544
+; MIR64-NEXT: BLR8 implicit $lr8, implicit $rm
+
+; ASM32-LABEL: .fprs_gprs_vecregs:
+
+; ASM32: stwu 1, -448(1)
+; ASM32-DAG: li [[FIXEDSTACK11:[0-9]+]], 32
+; ASM32-DAG: stxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK10:[0-9]+]], 48
+; ASM32-DAG: stxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK9:[0-9]+]], 64
+; ASM32-DAG: stxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK8:[0-9]+]], 80
+; ASM32-DAG: stxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK7:[0-9]+]], 96
+; ASM32-DAG: stxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK6:[0-9]+]], 112
+; ASM32-DAG: stxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK5:[0-9]+]], 128
+; ASM32-DAG: stxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK4:[0-9]+]], 144
+; ASM32-DAG: stxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK3:[0-9]+]], 160
+; ASM32-DAG: stxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK2:[0-9]+]], 176
+; ASM32-DAG: stxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK1:[0-9]+]], 192
+; ASM32-DAG: stxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Spill
+; ASM32-DAG: li [[FIXEDSTACK0:[0-9]+]], 208
+; ASM32-DAG: stxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Spill
+; ASM32-DAG: stw 14, 232(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 15, 236(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 16, 240(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 17, 244(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 18, 248(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 19, 252(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 20, 256(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 21, 260(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 22, 264(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 23, 268(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 24, 272(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 25, 276(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 26, 280(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 27, 284(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 28, 288(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 29, 292(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 30, 296(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 31, 300(1) # 4-byte Folded Spill
+; ASM32-DAG: stfd 14, 304(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 15, 312(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 16, 320(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 17, 328(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 18, 336(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 19, 344(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 20, 352(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 21, 360(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 22, 368(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 23, 376(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 24, 384(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 25, 392(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 26, 400(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 27, 408(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 28, 416(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 29, 424(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 30, 432(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 31, 440(1) # 8-byte Folded Spill
+
+; ASM32: #APP
+; ASM32-NEXT: #NO_APP
+
+; ASM32-DAG: lxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK1:[0-9]+]], 192
+; ASM32-DAG: lxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK2:[0-9]+]], 176
+; ASM32-DAG: lxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK3:[0-9]+]], 160
+; ASM32-DAG: lxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK4:[0-9]+]], 144
+; ASM32-DAG: lxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK5:[0-9]+]], 128
+; ASM32-DAG: lxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK6:[0-9]+]], 112
+; ASM32-DAG: lxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK7:[0-9]+]], 96
+; ASM32-DAG: lxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK8:[0-9]+]], 80
+; ASM32-DAG: lxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK9:[0-9]+]], 64
+; ASM32-DAG: lxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK10:[0-9]+]], 48
+; ASM32-DAG: lxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Reload
+; ASM32-DAG: li [[FIXEDSTACK11:[0-9]+]], 32
+; ASM32-DAG: lxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Reload
+; ASM32-DAG: lfd 31, 440(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 30, 432(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 29, 424(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 28, 416(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 27, 408(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 26, 400(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 25, 392(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 24, 384(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 23, 376(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 22, 368(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 21, 360(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 20, 352(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 19, 344(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 18, 336(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 17, 328(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 16, 320(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 15, 312(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 14, 304(1) # 8-byte Folded Reload
+; ASM32-DAG: lwz 31, 300(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 30, 296(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 29, 292(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 28, 288(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 27, 284(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 26, 280(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 25, 276(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 24, 272(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 23, 268(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 22, 264(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 21, 260(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 20, 256(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 19, 252(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 18, 248(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 17, 244(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 16, 240(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 15, 236(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 14, 232(1) # 4-byte Folded Reload
+
+; ASM32: addi 1, 1, 448
+; ASM32-NEXT: blr
; ASM64-LABEL: .fprs_gprs_vecregs:
-; ASM64: stdu 1, -544(1)
-; ASM64-DAG: li {{[0-9]+}}, 64
-; ASM64-DAG: std 14, 256(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 14, 400(1) # 8-byte Folded Spill
-; ASM64-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM64-DAG: li {{[0-9]+}}, 160
-; ASM64-DAG: std 25, 344(1) # 8-byte Folded Spill
-; ASM64-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM64-DAG: li {{[0-9]+}}, 240
-; ASM64-DAG: std 31, 392(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 21, 456(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 31, 536(1) # 8-byte Folded Spill
-; ASM64-DAG: stxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Spill
-; ASM64-DAG: #APP
-; ASM64-DAG: #NO_APP
-; ASM64-DAG: lxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM64-DAG: li {{[0-9]+}}, 160
-; ASM64-DAG: lfd 31, 536(1) # 8-byte Folded Reload
-; ASM64-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM64-DAG: li {{[0-9]+}}, 64
-; ASM64-DAG: lfd 21, 456(1) # 8-byte Folded Reload
-; ASM64-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload
-; ASM64-DAG: lfd 14, 400(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 31, 392(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 25, 344(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 14, 256(1) # 8-byte Folded Reload
-; ASM64-DAG: addi 1, 1, 544
-; ASM64: blr
+; ASM64: stdu 1, -544(1)
+; ASM64-DAG: li [[FIXEDSTACK11:[0-9]+]], 64
+; ASM64-DAG: stxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK10:[0-9]+]], 80
+; ASM64-DAG: stxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK9:[0-9]+]], 96
+; ASM64-DAG: stxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK8:[0-9]+]], 112
+; ASM64-DAG: stxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK7:[0-9]+]], 128
+; ASM64-DAG: stxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK6:[0-9]+]], 144
+; ASM64-DAG: stxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK5:[0-9]+]], 160
+; ASM64-DAG: stxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK4:[0-9]+]], 176
+; ASM64-DAG: stxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK3:[0-9]+]], 192
+; ASM64-DAG: stxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK2:[0-9]+]], 208
+; ASM64-DAG: stxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK1:[0-9]+]], 224
+; ASM64-DAG: stxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Spill
+; ASM64-DAG: li [[FIXEDSTACK0:[0-9]+]], 240
+; ASM64-DAG: stxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Spill
+; ASM64-DAG: std 14, 256(1) # 8-byte Folded Spill
+; ASM64-DAG: std 15, 264(1) # 8-byte Folded Spill
+; ASM64-DAG: std 16, 272(1) # 8-byte Folded Spill
+; ASM64-DAG: std 17, 280(1) # 8-byte Folded Spill
+; ASM64-DAG: std 18, 288(1) # 8-byte Folded Spill
+; ASM64-DAG: std 19, 296(1) # 8-byte Folded Spill
+; ASM64-DAG: std 20, 304(1) # 8-byte Folded Spill
+; ASM64-DAG: std 21, 312(1) # 8-byte Folded Spill
+; ASM64-DAG: std 22, 320(1) # 8-byte Folded Spill
+; ASM64-DAG: std 23, 328(1) # 8-byte Folded Spill
+; ASM64-DAG: std 24, 336(1) # 8-byte Folded Spill
+; ASM64-DAG: std 25, 344(1) # 8-byte Folded Spill
+; ASM64-DAG: std 26, 352(1) # 8-byte Folded Spill
+; ASM64-DAG: std 27, 360(1) # 8-byte Folded Spill
+; ASM64-DAG: std 28, 368(1) # 8-byte Folded Spill
+; ASM64-DAG: std 29, 376(1) # 8-byte Folded Spill
+; ASM64-DAG: std 30, 384(1) # 8-byte Folded Spill
+; ASM64-DAG: std 31, 392(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 14, 400(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 15, 408(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 16, 416(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 17, 424(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 18, 432(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 19, 440(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 20, 448(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 21, 456(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 22, 464(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 23, 472(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 24, 480(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 25, 488(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 26, 496(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 27, 504(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 28, 512(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 29, 520(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 30, 528(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 31, 536(1) # 8-byte Folded Spill
+
+; ASM64: #APP
+; ASM64-NEXT: #NO_APP
+
+; ASM64-DAG: lxvd2x 63, 1, [[FIXEDSTACK0]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK1:[0-9]+]], 224
+; ASM64-DAG: lxvd2x 62, 1, [[FIXEDSTACK1]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK2:[0-9]+]], 208
+; ASM64-DAG: lxvd2x 61, 1, [[FIXEDSTACK2]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK3:[0-9]+]], 192
+; ASM64-DAG: lxvd2x 60, 1, [[FIXEDSTACK3]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK4:[0-9]+]], 176
+; ASM64-DAG: lxvd2x 59, 1, [[FIXEDSTACK4]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK5:[0-9]+]], 160
+; ASM64-DAG: lxvd2x 58, 1, [[FIXEDSTACK5]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK6:[0-9]+]], 144
+; ASM64-DAG: lxvd2x 57, 1, [[FIXEDSTACK6]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK7:[0-9]+]], 128
+; ASM64-DAG: lxvd2x 56, 1, [[FIXEDSTACK7]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK8:[0-9]+]], 112
+; ASM64-DAG: lxvd2x 55, 1, [[FIXEDSTACK8]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK9:[0-9]+]], 96
+; ASM64-DAG: lxvd2x 54, 1, [[FIXEDSTACK9]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK10:[0-9]+]], 80
+; ASM64-DAG: lxvd2x 53, 1, [[FIXEDSTACK10]] # 16-byte Folded Reload
+; ASM64-DAG: li [[FIXEDSTACK11:[0-9]+]], 64
+; ASM64-DAG: lxvd2x 52, 1, [[FIXEDSTACK11]] # 16-byte Folded Reload
+; ASM64-DAG: lfd 31, 536(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 30, 528(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 29, 520(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 28, 512(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 27, 504(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 26, 496(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 25, 488(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 24, 480(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 23, 472(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 22, 464(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 21, 456(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 20, 448(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 19, 440(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 18, 432(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 17, 424(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 16, 416(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 15, 408(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 14, 400(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 31, 392(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 30, 384(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 29, 376(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 28, 368(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 27, 360(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 26, 352(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 25, 344(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 24, 336(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 23, 328(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 22, 320(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 21, 312(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 20, 304(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 19, 296(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 18, 288(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 17, 280(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 16, 272(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 15, 264(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 14, 256(1) # 8-byte Folded Reload
+
+; ASM64: addi 1, 1, 544
+; ASM64-NEXT: blr
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
index 45ec7357656bcb..cbca8918fc0554 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -14,7 +14,7 @@
; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
; RUN: FileCheck --check-prefix=ASM64 %s
-define dso_local void @vec_regs() {
+define dso_local void @vec_regs() #0 {
entry:
call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
ret void
@@ -62,25 +62,35 @@ define dso_local void @vec_regs() {
; ASM64-DAG: #NO_APP
; ASM64: blr
-define dso_local void @fprs_gprs_vecregs() {
- call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
+define dso_local void @fprs_gprs_vecregs() #0 {
+ call void asm sideeffect "", "~{r25},~{r28},~{r31},~{f21},~{f25},~{f31},~{v20},~{v26},~{v31}"()
ret void
}
; MIR32-LABEL: name: fprs_gprs_vecregs
-; MIR32: fixedStack:
-
-; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31
+; MIR32: liveins: $r25, $r26, $r27, $r28, $r29, $r30, $r31, $f21, $f22, $f23, $f24, $f25, $f26, $f27, $f28, $f29, $f30, $f31
; MIR32-NOT: STXVD2X killed $v20
; MIR32-NOT: STXVD2X killed $v26
; MIR32-NOT: STXVD2X killed $v31
-; MIR32-DAG: STW killed $r14, -216, $r1 :: (store (s32) into %fixed-stack.5, align 8)
-; MIR32-DAG: STW killed $r25, -172, $r1 :: (store (s32) into %fixed-stack.4)
-; MIR32-DAG: STW killed $r31, -148, $r1 :: (store (s32) into %fixed-stack.3)
-; MIR32-DAG: STFD killed $f14, -144, $r1 :: (store (s64) into %fixed-stack.2, align 16)
-; MIR32-DAG: STFD killed $f21, -88, $r1 :: (store (s64) into %fixed-stack.1)
+; MIR32-DAG: STW killed $r25, -116, $r1 :: (store (s32) into %fixed-stack.17)
+; MIR32-DAG: STW killed $r26, -112, $r1 :: (store (s32) into %fixed-stack.16, align 8)
+; MIR32-DAG: STW killed $r27, -108, $r1 :: (store (s32) into %fixed-stack.15)
+; MIR32-DAG: STW killed $r28, -104, $r1 :: (store (s32) into %fixed-stack.14, align 16)
+; MIR32-DAG: STW killed $r29, -100, $r1 :: (store (s32) into %fixed-stack.13)
+; MIR32-DAG: STW killed $r30, -96, $r1 :: (store (s32) into %fixed-stack.12, align 8)
+; MIR32-DAG: STW killed $r31, -92, $r1 :: (store (s32) into %fixed-stack.11)
+; MIR32-DAG: STFD killed $f21, -88, $r1 :: (store (s64) into %fixed-stack.10)
+; MIR32-DAG: STFD killed $f22, -80, $r1 :: (store (s64) into %fixed-stack.9, align 16)
+; MIR32-DAG: STFD killed $f23, -72, $r1 :: (store (s64) into %fixed-stack.8)
+; MIR32-DAG: STFD killed $f24, -64, $r1 :: (store (s64) into %fixed-stack.7, align 16)
+; MIR32-DAG: STFD killed $f25, -56, $r1 :: (store (s64) into %fixed-stack.6)
+; MIR32-DAG: STFD killed $f26, -48, $r1 :: (store (s64) into %fixed-stack.5, align 16)
+; MIR32-DAG: STFD killed $f27, -40, $r1 :: (store (s64) into %fixed-stack.4)
+; MIR32-DAG: STFD killed $f28, -32, $r1 :: (store (s64) into %fixed-stack.3, align 16)
+; MIR32-DAG: STFD killed $f29, -24, $r1 :: (store (s64) into %fixed-stack.2)
+; MIR32-DAG: STFD killed $f30, -16, $r1 :: (store (s64) into %fixed-stack.1, align 16)
; MIR32-DAG: STFD killed $f31, -8, $r1 :: (store (s64) into %fixed-stack.0)
; MIR32-LABEL: INLINEASM
@@ -88,28 +98,50 @@ define dso_local void @fprs_gprs_vecregs() {
; MIR32-NOT: $v20 = LXVD2X
; MIR32-NOT: $v26 = LXVD2X
; MIR32-NOT: $v31 = LXVD2X
-; MIR32-DAG: $r14 = LWZ -216, $r1 :: (load (s32) from %fixed-stack.5, align 8)
-; MIR32-DAG: $r25 = LWZ -172, $r1 :: (load (s32) from %fixed-stack.4)
-; MIR32-DAG: $r31 = LWZ -148, $r1 :: (load (s32) from %fixed-stack.3)
-; MIR32-DAG: $f14 = LFD -144, $r1 :: (load (s64) from %fixed-stack.2, align 16)
-; MIR32-DAG: $f21 = LFD -88, $r1 :: (load (s64) from %fixed-stack.1)
; MIR32-DAG: $f31 = LFD -8, $r1 :: (load (s64) from %fixed-stack.0)
-; MIR32-DAG: BLR implicit $lr, implicit $rm
+; MIR32-DAG: $f30 = LFD -16, $r1 :: (load (s64) from %fixed-stack.1, align 16)
+; MIR32-DAG: $f29 = LFD -24, $r1 :: (load (s64) from %fixed-stack.2)
+; MIR32-DAG: $f28 = LFD -32, $r1 :: (load (s64) from %fixed-stack.3, align 16)
+; MIR32-DAG: $f27 = LFD -40, $r1 :: (load (s64) from %fixed-stack.4)
+; MIR32-DAG: $f26 = LFD -48, $r1 :: (load (s64) from %fixed-stack.5, align 16)
+; MIR32-DAG: $f25 = LFD -56, $r1 :: (load (s64) from %fixed-stack.6)
+; MIR32-DAG: $f24 = LFD -64, $r1 :: (load (s64) from %fixed-stack.7, align 16)
+; MIR32-DAG: $f23 = LFD -72, $r1 :: (load (s64) from %fixed-stack.8)
+; MIR32-DAG: $f22 = LFD -80, $r1 :: (load (s64) from %fixed-stack.9, align 16)
+; MIR32-DAG: $f21 = LFD -88, $r1 :: (load (s64) from %fixed-stack.10)
+; MIR32-DAG: $r31 = LWZ -92, $r1 :: (load (s32) from %fixed-stack.11)
+; MIR32-DAG: $r30 = LWZ -96, $r1 :: (load (s32) from %fixed-stack.12, align 8)
+; MIR32-DAG: $r29 = LWZ -100, $r1 :: (load (s32) from %fixed-stack.13)
+; MIR32-DAG: $r28 = LWZ -104, $r1 :: (load (s32) from %fixed-stack.14, align 16)
+; MIR32-DAG: $r27 = LWZ -108, $r1 :: (load (s32) from %fixed-stack.15)
+; MIR32-DAG: $r26 = LWZ -112, $r1 :: (load (s32) from %fixed-stack.16, align 8)
+; MIR32-DAG: $r25 = LWZ -116, $r1 :: (load (s32) from %fixed-stack.17)
+; MIR32: BLR implicit $lr, implicit $rm
; MIR64-LABEL: name: fprs_gprs_vecregs
-; MIR64: fixedStack:
-
-; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31
+; MIR64: liveins: $x25, $x26, $x27, $x28, $x29, $x30, $x31, $f21, $f22, $f23, $f24, $f25, $f26, $f27, $f28, $f29, $f30, $f31
; MIR64-NOT: STXVD2X killed $v20
; MIR64-NOT: STXVD2X killed $v26
; MIR64-NOT: STXVD2X killed $v31
-; MIR64-DAG: STD killed $x14, -288, $x1 :: (store (s64) into %fixed-stack.5, align 16)
-; MIR64-DAG: STD killed $x25, -200, $x1 :: (store (s64) into %fixed-stack.4)
-; MIR64-DAG: STD killed $x31, -152, $x1 :: (store (s64) into %fixed-stack.3)
-; MIR64-DAG: STFD killed $f14, -144, $x1 :: (store (s64) into %fixed-stack.2, align 16)
-; MIR64-DAG: STFD killed $f21, -88, $x1 :: (store (s64) into %fixed-stack.1)
+; MIR64-DAG: STD killed $x25, -144, $x1 :: (store (s64) into %fixed-stack.17)
+; MIR64-DAG: STD killed $x26, -136, $x1 :: (store (s64) into %fixed-stack.16, align 16)
+; MIR64-DAG: STD killed $x27, -128, $x1 :: (store (s64) into %fixed-stack.15)
+; MIR64-DAG: STD killed $x28, -120, $x1 :: (store (s64) into %fixed-stack.14, align 16)
+; MIR64-DAG: STD killed $x29, -112, $x1 :: (store (s64) into %fixed-stack.13)
+; MIR64-DAG: STD killed $x30, -104, $x1 :: (store (s64) into %fixed-stack.12, align 16)
+; MIR64-DAG: STD killed $x31, -96, $x1 :: (store (s64) into %fixed-stack.11)
+; MIR64-DAG: STFD killed $f21, -88, $x1 :: (store (s64) into %fixed-stack.10)
+; MIR64-DAG: STFD killed $f22, -80, $x1 :: (store (s64) into %fixed-stack.9, align 16)
+; MIR64-DAG: STFD killed $f23, -72, $x1 :: (store (s64) into %fixed-stack.8)
+; MIR64-DAG: STFD killed $f24, -64, $x1 :: (store (s64) into %fixed-stack.7, align 16)
+; MIR64-DAG: STFD killed $f25, -56, $x1 :: (store (s64) into %fixed-stack.6)
+; MIR64-DAG: STFD killed $f26, -48, $x1 :: (store (s64) into %fixed-stack.5, align 16)
+; MIR64-DAG: STFD killed $f27, -40, $x1 :: (store (s64) into %fixed-stack.4)
+; MIR64-DAG: STFD killed $f28, -32, $x1 :: (store (s64) into %fixed-stack.3, align 16)
+; MIR64-DAG: STFD killed $f29, -24, $x1 :: (store (s64) into %fixed-stack.2)
+; MIR64-DAG: STFD killed $f30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
; MIR64-DAG: STFD killed $f31, -8, $x1 :: (store (s64) into %fixed-stack.0)
; MIR64-LABEL: INLINEASM
@@ -117,12 +149,25 @@ define dso_local void @fprs_gprs_vecregs() {
; MIR64-NOT: $v20 = LXVD2X
; MIR64-NOT: $v26 = LXVD2X
; MIR64-NOT: $v31 = LXVD2X
-; MIR64-DAG: $x14 = LD -288, $x1 :: (load (s64) from %fixed-stack.5, align 16)
-; MIR64-DAG: $x25 = LD -200, $x1 :: (load (s64) from %fixed-stack.4)
-; MIR64-DAG: $x31 = LD -152, $x1 :: (load (s64) from %fixed-stack.3)
-; MIR64-DAG: $f14 = LFD -144, $x1 :: (load (s64) from %fixed-stack.2, align 16)
-; MIR64-DAG: $f21 = LFD -88, $x1 :: (load (s64) from %fixed-stack.1)
; MIR64-DAG: $f31 = LFD -8, $x1 :: (load (s64) from %fixed-stack.0)
+; MIR64-DAG: $f30 = LFD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+; MIR64-DAG: $f29 = LFD -24, $x1 :: (load (s64) from %fixed-stack.2)
+; MIR64-DAG: $f28 = LFD -32, $x1 :: (load (s64) from %fixed-stack.3, align 16)
+; MIR64-DAG: $f27 = LFD -40, $x1 :: (load (s64) from %fixed-stack.4)
+; MIR64-DAG: $f26 = LFD -48, $x1 :: (load (s64) from %fixed-stack.5, align 16)
+; MIR64-DAG: $f25 = LFD -56, $x1 :: (load (s64) from %fixed-stack.6)
+; MIR64-DAG: $f24 = LFD -64, $x1 :: (load (s64) from %fixed-stack.7, align 16)
+; MIR64-DAG: $f23 = LFD -72, $x1 :: (load (s64) from %fixed-stack.8)
+; MIR64-DAG: $f22 = LFD -80, $x1 :: (load (s64) from %fixed-stack.9, align 16)
+; MIR64-DAG: $f21 = LFD -88, $x1 :: (load (s64) from %fixed-stack.10)
+; MIR64-DAG: $x31 = LD -96, $x1 :: (load (s64) from %fixed-stack.11)
+; MIR64-DAG: $x30 = LD -104, $x1 :: (load (s64) from %fixed-stack.12, align 16)
+; MIR64-DAG: $x29 = LD -112, $x1 :: (load (s64) from %fixed-stack.13)
+; MIR64-DAG: $x28 = LD -120, $x1 :: (load (s64) from %fixed-stack.14, align 16)
+; MIR64-DAG: $x27 = LD -128, $x1 :: (load (s64) from %fixed-stack.15)
+; MIR64-DAG: $x26 = LD -136, $x1 :: (load (s64) from %fixed-stack.16, align 16)
+; MIR64-DAG: $x25 = LD -144, $x1 :: (load (s64) from %fixed-stack.17)
+
; MIR64: BLR8 implicit $lr8, implicit $rm
;; We don't have -ppc-full-reg-names on AIX so can't reliably check-not for
@@ -130,41 +175,90 @@ define dso_local void @fprs_gprs_vecregs() {
; ASM32-LABEL: .fprs_gprs_vecregs:
-; ASM32-DAG: stw 14, -216(1) # 4-byte Folded Spill
-; ASM32-DAG: stw 25, -172(1) # 4-byte Folded Spill
-; ASM32-DAG: stw 31, -148(1) # 4-byte Folded Spill
-; ASM32-DAG: stfd 14, -144(1) # 8-byte Folded Spill
-; ASM32-DAG: stfd 21, -88(1) # 8-byte Folded Spill
-; ASM32-DAG: stfd 31, -8(1) # 8-byte Folded Spill
-; ASM32-DAG: #APP
-; ASM32-DAG: #NO_APP
-; ASM32-DAG: lfd 31, -8(1) # 8-byte Folded Reload
-; ASM32-DAG: lfd 21, -88(1) # 8-byte Folded Reload
-; ASM32-DAG: lfd 14, -144(1) # 8-byte Folded Reload
-; ASM32-DAG: lwz 31, -148(1) # 4-byte Folded Reload
-; ASM32-DAG: lwz 25, -172(1) # 4-byte Folded Reload
-; ASM32-DAG: lwz 14, -216(1) # 4-byte Folded Reload
+; ASM32-DAG: stw 25, -116(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 26, -112(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 27, -108(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 28, -104(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 29, -100(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 30, -96(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 31, -92(1) # 4-byte Folded Spill
+; ASM32-DAG: stfd 21, -88(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 22, -80(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 23, -72(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 24, -64(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 25, -56(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 26, -48(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 27, -40(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 28, -32(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 29, -24(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 30, -16(1) # 8-byte Folded Spill
+; ASM32-DAG: stfd 31, -8(1) # 8-byte Folded Spill
+; ASM32: #APP
+; ASM32-NEXT: #NO_APP
+; ASM32-DAG: lfd 31, -8(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 30, -16(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 29, -24(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 28, -32(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 27, -40(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 26, -48(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 25, -56(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 24, -64(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 23, -72(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 22, -80(1) # 8-byte Folded Reload
+; ASM32-DAG: lfd 21, -88(1) # 8-byte Folded Reload
+; ASM32-DAG: lwz 31, -92(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 30, -96(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 29, -100(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 28, -104(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 27, -108(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 26, -112(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 25, -116(1) # 4-byte Folded Reload
; ASM32: blr
; ASM64-LABEL: .fprs_gprs_vecregs:
-; ASM64-DAG: std 14, -288(1) # 8-byte Folded Spill
-; ASM64-DAG: std 25, -200(1) # 8-byte Folded Spill
-; ASM64-DAG: std 31, -152(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 14, -144(1) # 8-byte Folded Spill
+; ASM64-DAG: std 25, -144(1) # 8-byte Folded Spill
+; ASM64-DAG: std 26, -136(1) # 8-byte Folded Spill
+; ASM64-DAG: std 27, -128(1) # 8-byte Folded Spill
+; ASM64-DAG: std 28, -120(1) # 8-byte Folded Spill
+; ASM64-DAG: std 29, -112(1) # 8-byte Folded Spill
+; ASM64-DAG: std 30, -104(1) # 8-byte Folded Spill
+; ASM64-DAG: std 31, -96(1) # 8-byte Folded Spill
; ASM64-DAG: stfd 21, -88(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 22, -80(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 23, -72(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 24, -64(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 25, -56(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 26, -48(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 27, -40(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 28, -32(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 29, -24(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 30, -16(1) # 8-byte Folded Spill
; ASM64-DAG: stfd 31, -8(1) # 8-byte Folded Spill
-; ASM64-DAG: #APP
-; ASM64-DAG: #NO_APP
+; ASM64: #APP
+; ASM64-NEXT: #NO_APP
; ASM64-DAG: lfd 31, -8(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 30, -16(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 29, -24(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 28, -32(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 27, -40(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 26, -48(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 25, -56(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 24, -64(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 23, -72(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 22, -80(1) # 8-byte Folded Reload
; ASM64-DAG: lfd 21, -88(1) # 8-byte Folded Reload
-; ASM64-DAG: lfd 14, -144(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 31, -152(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 25, -200(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 14, -288(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 31, -96(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 30, -104(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 29, -112(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 28, -120(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 27, -128(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 26, -136(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 25, -144(1) # 8-byte Folded Reload
+
; ASM64: blr
-define dso_local void @all_fprs_and_vecregs() {
+define dso_local void @all_fprs_and_vecregs() #0 {
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6}~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}"()
ret void
}
@@ -199,3 +293,4 @@ define dso_local void @all_fprs_and_vecregs() {
; MIR64-NOT: $v29
; MIR64-NOT: $v30
; MIR64-NOT: $v31
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr.ll b/llvm/test/CodeGen/PowerPC/aix-csr.ll
index a9a85c8be5a105..ac62595e68b868 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr.ll
@@ -20,77 +20,260 @@ entry:
; MIR64: name: gprs_only
; MIR64-LABEL: fixedStack:
-; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x30', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x22', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x16', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 3, type: spill-slot, offset: -32, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 4, type: spill-slot, offset: -40, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 5, type: spill-slot, offset: -48, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 6, type: spill-slot, offset: -56, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 7, type: spill-slot, offset: -64, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 8, type: spill-slot, offset: -72, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 9, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 10, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 11, type: spill-slot, offset: -96, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 12, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x19', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 13, type: spill-slot, offset: -112, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x18', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 14, type: spill-slot, offset: -120, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x17', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 15, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x16', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
; MIR64-NEXT: stack: []
; MIR32: name: gprs_only
; MIR32-LABEL: fixedStack:
-; MIR32: - { id: 0, type: spill-slot, offset: -8, size: 4, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r30', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -40, size: 4, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r22', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -64, size: 4, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r16', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -28, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -32, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -36, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 9, type: spill-slot, offset: -40, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 10, type: spill-slot, offset: -44, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 11, type: spill-slot, offset: -48, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 12, type: spill-slot, offset: -52, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r19', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 13, type: spill-slot, offset: -56, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r18', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 14, type: spill-slot, offset: -60, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r17', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 15, type: spill-slot, offset: -64, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r16', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
; MIR32-NEXT: stack: []
-; MIR64: liveins: $x3, $x16, $x22, $x30
-
-; MIR64-DAG: STD killed $x16, -128, $x1 :: (store (s64) into %fixed-stack.2, align 16)
-; MIR64-DAG: STD killed $x22, -80, $x1 :: (store (s64) into %fixed-stack.1, align 16)
-; MIR64-DAG: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.0, align 16)
+; MIR64: liveins: $x3, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
+
+; MIR64-DAG: STD killed $x16, -128, $x1 :: (store (s64) into %fixed-stack.15, align 16)
+; MIR64-DAG: STD killed $x17, -120, $x1 :: (store (s64) into %fixed-stack.14)
+; MIR64-DAG: STD killed $x18, -112, $x1 :: (store (s64) into %fixed-stack.13, align 16)
+; MIR64-DAG: STD killed $x19, -104, $x1 :: (store (s64) into %fixed-stack.12)
+; MIR64-DAG: STD killed $x20, -96, $x1 :: (store (s64) into %fixed-stack.11, align 16)
+; MIR64-DAG: STD killed $x21, -88, $x1 :: (store (s64) into %fixed-stack.10)
+; MIR64-DAG: STD killed $x22, -80, $x1 :: (store (s64) into %fixed-stack.9, align 16)
+; MIR64-DAG: STD killed $x23, -72, $x1 :: (store (s64) into %fixed-stack.8)
+; MIR64-DAG: STD killed $x24, -64, $x1 :: (store (s64) into %fixed-stack.7, align 16)
+; MIR64-DAG: STD killed $x25, -56, $x1 :: (store (s64) into %fixed-stack.6)
+; MIR64-DAG: STD killed $x26, -48, $x1 :: (store (s64) into %fixed-stack.5, align 16)
+; MIR64-DAG: STD killed $x27, -40, $x1 :: (store (s64) into %fixed-stack.4)
+; MIR64-DAG: STD killed $x28, -32, $x1 :: (store (s64) into %fixed-stack.3, align 16)
+; MIR64-DAG: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
+; MIR64-DAG: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
+; MIR64-DAG: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
; MIR64: INLINEASM
-; MIR64-DAG: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.0, align 16)
-; MIR64-DAG: $x22 = LD -80, $x1 :: (load (s64) from %fixed-stack.1, align 16)
-; MIR64-DAG: $x16 = LD -128, $x1 :: (load (s64) from %fixed-stack.2, align 16)
-; MIR64: BLR8 implicit $lr8, implicit $rm, implicit $x3
-
-; MIR32: liveins: $r3, $r16, $r22, $r30
+; MIR64-DAG: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
+; MIR64-DAG: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+; MIR64-DAG: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
+; MIR64-DAG: $x28 = LD -32, $x1 :: (load (s64) from %fixed-stack.3, align 16)
+; MIR64-DAG: $x27 = LD -40, $x1 :: (load (s64) from %fixed-stack.4)
+; MIR64-DAG: $x26 = LD -48, $x1 :: (load (s64) from %fixed-stack.5, align 16)
+; MIR64-DAG: $x25 = LD -56, $x1 :: (load (s64) from %fixed-stack.6)
+; MIR64-DAG: $x24 = LD -64, $x1 :: (load (s64) from %fixed-stack.7, align 16)
+; MIR64-DAG: $x23 = LD -72, $x1 :: (load (s64) from %fixed-stack.8)
+; MIR64-DAG: $x22 = LD -80, $x1 :: (load (s64) from %fixed-stack.9, align 16)
+; MIR64-DAG: $x21 = LD -88, $x1 :: (load (s64) from %fixed-stack.10)
+; MIR64-DAG: $x20 = LD -96, $x1 :: (load (s64) from %fixed-stack.11, align 16)
+; MIR64-DAG: $x19 = LD -104, $x1 :: (load (s64) from %fixed-stack.12)
+; MIR64-DAG: $x18 = LD -112, $x1 :: (load (s64) from %fixed-stack.13, align 16)
+; MIR64-DAG: $x17 = LD -120, $x1 :: (load (s64) from %fixed-stack.14)
+; MIR64-DAG: $x16 = LD -128, $x1 :: (load (s64) from %fixed-stack.15, align 16)
+; MIR64: BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+
+; MIR32: liveins: $r3, $r16, $r17, $r18, $r19, $r20, $r21, $r22, $r23, $r24, $r25, $r26, $r27, $r28, $r29, $r30, $r31
+
+; MIR32-DAG: STW killed $r16, -64, $r1 :: (store (s32) into %fixed-stack.15, align 16)
+; MIR32-DAG: STW killed $r17, -60, $r1 :: (store (s32) into %fixed-stack.14)
+; MIR32-DAG: STW killed $r18, -56, $r1 :: (store (s32) into %fixed-stack.13, align 8)
+; MIR32-DAG: STW killed $r19, -52, $r1 :: (store (s32) into %fixed-stack.12)
+; MIR32-DAG: STW killed $r20, -48, $r1 :: (store (s32) into %fixed-stack.11, align 16)
+; MIR32-DAG: STW killed $r21, -44, $r1 :: (store (s32) into %fixed-stack.10)
+; MIR32-DAG: STW killed $r22, -40, $r1 :: (store (s32) into %fixed-stack.9, align 8)
+; MIR32-DAG: STW killed $r23, -36, $r1 :: (store (s32) into %fixed-stack.8)
+; MIR32-DAG: STW killed $r24, -32, $r1 :: (store (s32) into %fixed-stack.7, align 16)
+; MIR32-DAG: STW killed $r25, -28, $r1 :: (store (s32) into %fixed-stack.6)
+; MIR32-DAG: STW killed $r26, -24, $r1 :: (store (s32) into %fixed-stack.5, align 8)
+; MIR32-DAG: STW killed $r27, -20, $r1 :: (store (s32) into %fixed-stack.4)
+; MIR32-DAG: STW killed $r28, -16, $r1 :: (store (s32) into %fixed-stack.3, align 16)
+; MIR32-DAG: STW killed $r29, -12, $r1 :: (store (s32) into %fixed-stack.2)
+; MIR32-DAG: STW killed $r30, -8, $r1 :: (store (s32) into %fixed-stack.1, align 8)
+; MIR32-DAG: STW killed $r31, -4, $r1 :: (store (s32) into %fixed-stack.0)
-; MIR32-DAG: STW killed $r16, -64, $r1 :: (store (s32) into %fixed-stack.2, align 16)
-; MIR32-DAG: STW killed $r22, -40, $r1 :: (store (s32) into %fixed-stack.1, align 8)
-; MIR32-DAG: STW killed $r30, -8, $r1 :: (store (s32) into %fixed-stack.0, align 8)
-
-; MIR32: INLINEASM
+; MIR32: INLINEASM
-; MIR32-DAG: $r30 = LWZ -8, $r1 :: (load (s32) from %fixed-stack.0, align 8)
-; MIR32-DAG: $r22 = LWZ -40, $r1 :: (load (s32) from %fixed-stack.1, align 8)
-; MIR32-DAG: $r16 = LWZ -64, $r1 :: (load (s32) from %fixed-stack.2, align 16)
-; MIR32: BLR implicit $lr, implicit $rm, implicit $r3
+; MIR32-DAG: $r31 = LWZ -4, $r1 :: (load (s32) from %fixed-stack.0)
+; MIR32-DAG: $r30 = LWZ -8, $r1 :: (load (s32) from %fixed-stack.1, align 8)
+; MIR32-DAG: $r29 = LWZ -12, $r1 :: (load (s32) from %fixed-stack.2)
+; MIR32-DAG: $r28 = LWZ -16, $r1 :: (load (s32) from %fixed-stack.3, align 16)
+; MIR32-DAG: $r27 = LWZ -20, $r1 :: (load (s32) from %fixed-stack.4)
+; MIR32-DAG: $r26 = LWZ -24, $r1 :: (load (s32) from %fixed-stack.5, align 8)
+; MIR32-DAG: $r25 = LWZ -28, $r1 :: (load (s32) from %fixed-stack.6)
+; MIR32-DAG: $r24 = LWZ -32, $r1 :: (load (s32) from %fixed-stack.7, align 16)
+; MIR32-DAG: $r23 = LWZ -36, $r1 :: (load (s32) from %fixed-stack.8)
+; MIR32-DAG: $r22 = LWZ -40, $r1 :: (load (s32) from %fixed-stack.9, align 8)
+; MIR32-DAG: $r21 = LWZ -44, $r1 :: (load (s32) from %fixed-stack.10)
+; MIR32-DAG: $r20 = LWZ -48, $r1 :: (load (s32) from %fixed-stack.11, align 16)
+; MIR32-DAG: $r19 = LWZ -52, $r1 :: (load (s32) from %fixed-stack.12)
+; MIR32-DAG: $r18 = LWZ -56, $r1 :: (load (s32) from %fixed-stack.13, align 8)
+; MIR32-DAG: $r17 = LWZ -60, $r1 :: (load (s32) from %fixed-stack.14)
+; MIR32-DAG: $r16 = LWZ -64, $r1 :: (load (s32) from %fixed-stack.15, align 16)
+; MIR32: BLR implicit $lr, implicit $rm, implicit $r3
; ASM64-LABEL: .gprs_only:
-; ASM64-DAG: std 16, -128(1) # 8-byte Folded Spill
-; ASM64-DAG: std 22, -80(1) # 8-byte Folded Spill
-; ASM64-DAG: std 30, -16(1) # 8-byte Folded Spill
-; ASM64: #APP
-; ASM64-DAG: ld 30, -16(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 22, -80(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 16, -128(1) # 8-byte Folded Reload
+; ASM64-DAG: std 16, -128(1) # 8-byte Folded Spill
+; ASM64-DAG: std 17, -120(1) # 8-byte Folded Spill
+; ASM64-DAG: std 18, -112(1) # 8-byte Folded Spill
+; ASM64-DAG: std 19, -104(1) # 8-byte Folded Spill
+; ASM64-DAG: std 20, -96(1) # 8-byte Folded Spill
+; ASM64-DAG: std 21, -88(1) # 8-byte Folded Spill
+; ASM64-DAG: std 22, -80(1) # 8-byte Folded Spill
+; ASM64-DAG: std 23, -72(1) # 8-byte Folded Spill
+; ASM64-DAG: std 24, -64(1) # 8-byte Folded Spill
+; ASM64-DAG: std 25, -56(1) # 8-byte Folded Spill
+; ASM64-DAG: std 26, -48(1) # 8-byte Folded Spill
+; ASM64-DAG: std 27, -40(1) # 8-byte Folded Spill
+; ASM64-DAG: std 28, -32(1) # 8-byte Folded Spill
+; ASM64-DAG: std 29, -24(1) # 8-byte Folded Spill
+; ASM64-DAG: std 30, -16(1) # 8-byte Folded Spill
+; ASM64-DAG: std 31, -8(1) # 8-byte Folded Spill
+; ASM64: #APP
+; AMS64-DAG: ld 31, -8(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 30, -16(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 29, -24(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 28, -32(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 27, -40(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 26, -48(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 25, -56(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 24, -64(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 23, -72(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 22, -80(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 21, -88(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 20, -96(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 19, -104(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 18, -112(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 17, -120(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 16, -128(1) # 8-byte Folded Reload
; ASM64: blr
; ASM32-LABEL: .gprs_only:
-; ASM32-DAG: stw 16, -64(1) # 4-byte Folded Spill
-; ASM32-DAG: stw 22, -40(1) # 4-byte Folded Spill
-; ASM32-DAG: stw 30, -8(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 16, -64(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 17, -60(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 18, -56(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 19, -52(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 20, -48(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 21, -44(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 22, -40(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 23, -36(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 24, -32(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 25, -28(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 26, -24(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 27, -20(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 28, -16(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 29, -12(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 30, -8(1) # 4-byte Folded Spill
+; ASM32-DAG: stw 31, -4(1) # 4-byte Folded Spill
; ASM32: #APP
-; ASM32-DAG: lwz 30, -8(1) # 4-byte Folded Reload
-; ASM32-DAG: lwz 22, -40(1) # 4-byte Folded Reload
-; ASM32-DAG: lwz 16, -64(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 31, -4(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 30, -8(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 29, -12(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 28, -16(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 27, -20(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 26, -24(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 25, -28(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 24, -32(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 23, -36(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 22, -40(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 21, -44(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 20, -48(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 19, -52(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 18, -56(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 17, -60(1) # 4-byte Folded Reload
+; ASM32-DAG: lwz 16, -64(1) # 4-byte Folded Reload
; ASM32-DAG: blr
@@ -104,112 +287,403 @@ define dso_local double @fprs_and_gprs(i32 signext %i) {
; MIR64: name: fprs_and_gprs
; MIR64-LABEL: fixedStack:
-; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 3, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 4, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 5, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR64-NEXT: - { id: 6, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
-; MIR64-NEXT: callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
-; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 3, type: spill-slot, offset: -32, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 4, type: spill-slot, offset: -40, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 5, type: spill-slot, offset: -48, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 6, type: spill-slot, offset: -56, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 7, type: spill-slot, offset: -64, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 8, type: spill-slot, offset: -72, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 9, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 10, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 11, type: spill-slot, offset: -96, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 12, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 13, type: spill-slot, offset: -112, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f18', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 14, type: spill-slot, offset: -120, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f17', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 15, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f16', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 16, type: spill-slot, offset: -136, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f15', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 17, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 18, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 19, type: spill-slot, offset: -160, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 20, type: spill-slot, offset: -168, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x29', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 21, type: spill-slot, offset: -176, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x28', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 22, type: spill-slot, offset: -184, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x27', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 23, type: spill-slot, offset: -192, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 24, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 25, type: spill-slot, offset: -208, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x24', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 26, type: spill-slot, offset: -216, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x23', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 27, type: spill-slot, offset: -224, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 28, type: spill-slot, offset: -232, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 29, type: spill-slot, offset: -240, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 30, type: spill-slot, offset: -248, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x19', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 31, type: spill-slot, offset: -256, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x18', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 32, type: spill-slot, offset: -264, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x17', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 33, type: spill-slot, offset: -272, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x16', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 34, type: spill-slot, offset: -280, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x15', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT: - { id: 35, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT: callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' }
; MIR64-NEXT: stack: []
; MIR32: name: fprs_and_gprs
; MIR32-LABEL: fixedStack:
-; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
-; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -220, size: 4, alignment: 4, stack-id: default,
-; MIR32-NEXT: callee-saved-register: '$r13', callee-saved-restored: true, debug-info-variable: '',
-; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -32, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -40, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -48, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -56, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -64, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -72, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 9, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 10, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 11, type: spill-slot, offset: -96, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 12, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 13, type: spill-slot, offset: -112, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f18', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 14, type: spill-slot, offset: -120, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f17', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 15, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f16', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 16, type: spill-slot, offset: -136, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f15', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 17, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 18, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 19, type: spill-slot, offset: -152, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 20, type: spill-slot, offset: -156, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r29', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 21, type: spill-slot, offset: -160, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r28', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 22, type: spill-slot, offset: -164, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r27', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 23, type: spill-slot, offset: -168, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 24, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 25, type: spill-slot, offset: -176, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r24', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 26, type: spill-slot, offset: -180, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r23', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 27, type: spill-slot, offset: -184, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 28, type: spill-slot, offset: -188, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 29, type: spill-slot, offset: -192, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 30, type: spill-slot, offset: -196, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r19', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 31, type: spill-slot, offset: -200, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r18', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 32, type: spill-slot, offset: -204, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r17', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 33, type: spill-slot, offset: -208, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r16', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 34, type: spill-slot, offset: -212, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r15', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 35, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT: - { id: 36, type: spill-slot, offset: -220, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT: callee-saved-register: '$r13', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
; MIR32-NEXT: stack: []
-; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31
+; MIR64: liveins: $x3, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31, $f14, $f15, $f16, $f17, $f18, $f19, $f20, $f21, $f22, $f23, $f24, $f25, $f26, $f27, $f28, $f29, $f30, $f31
; MIR64: $x0 = MFLR8 implicit $lr8
; MIR64-NEXT: $x1 = STDU $x1, -400, $x1
; MIR64-NEXT: STD killed $x0, 416, $x1
-; MIR64-DAG: STD killed $x14, 112, $x1 :: (store (s64) into %fixed-stack.6, align 16)
-; MIR64-DAG: STD killed $x25, 200, $x1 :: (store (s64) into %fixed-stack.5)
-; MIR64-DAG: STD killed $x31, 248, $x1 :: (store (s64) into %fixed-stack.4)
-; MIR64-DAG: STFD killed $f14, 256, $x1 :: (store (s64) into %fixed-stack.3, align 16)
-; MIR64-DAG: STFD killed $f19, 296, $x1 :: (store (s64) into %fixed-stack.2)
-; MIR64-DAG: STFD killed $f21, 312, $x1 :: (store (s64) into %fixed-stack.1)
+; MIR64-DAG: STD killed $x14, 112, $x1 :: (store (s64) into %fixed-stack.35, align 16)
+; MIR64-DAG: STD killed $x15, 120, $x1 :: (store (s64) into %fixed-stack.34)
+; MIR64-DAG: STD killed $x16, 128, $x1 :: (store (s64) into %fixed-stack.33, align 16)
+; MIR64-DAG: STD killed $x17, 136, $x1 :: (store (s64) into %fixed-stack.32)
+; MIR64-DAG: STD killed $x18, 144, $x1 :: (store (s64) into %fixed-stack.31, align 16)
+; MIR64-DAG: STD killed $x19, 152, $x1 :: (store (s64) into %fixed-stack.30)
+; MIR64-DAG: STD killed $x20, 160, $x1 :: (store (s64) into %fixed-stack.29, align 16)
+; MIR64-DAG: STD killed $x21, 168, $x1 :: (store (s64) into %fixed-stack.28)
+; MIR64-DAG: STD killed $x22, 176, $x1 :: (store (s64) into %fixed-stack.27, align 16)
+; MIR64-DAG: STD killed $x23, 184, $x1 :: (store (s64) into %fixed-stack.26)
+; MIR64-DAG: STD killed $x24, 192, $x1 :: (store (s64) into %fixed-stack.25, align 16)
+; MIR64-DAG: STD killed $x25, 200, $x1 :: (store (s64) into %fixed-stack.24)
+; MIR64-DAG: STD killed $x26, 208, $x1 :: (store (s64) into %fixed-stack.23, align 16)
+; MIR64-DAG: STD killed $x27, 216, $x1 :: (store (s64) into %fixed-stack.22)
+; MIR64-DAG: STD killed $x28, 224, $x1 :: (store (s64) into %fixed-stack.21, align 16)
+; MIR64-DAG: STD killed $x29, 232, $x1 :: (store (s64) into %fixed-stack.20)
+; MIR64-DAG: STD killed $x30, 240, $x1 :: (store (s64) into %fixed-stack.19, align 16)
+; MIR64-DAG: STD killed $x31, 248, $x1 :: (store (s64) into %fixed-stack.18)
+; MIR64-DAG: STFD killed $f14, 256, $x1 :: (store (s64) into %fixed-stack.17, align 16)
+; MIR64-DAG: STFD killed $f15, 264, $x1 :: (store (s64) into %fixed-stack.16)
+; MIR64-DAG: STFD killed $f16, 272, $x1 :: (store (s64) into %fixed-stack.15, align 16)
+; MIR64-DAG: STFD killed $f17, 280, $x1 :: (store (s64) into %fixed-stack.14)
+; MIR64-DAG: STFD killed $f18, 288, $x1 :: (store (s64) into %fixed-stack.13, align 16)
+; MIR64-DAG: STFD killed $f19, 296, $x1 :: (store (s64) into %fixed-stack.12)
+; MIR64-DAG: STFD killed $f20, 304, $x1 :: (store (s64) into %fixed-stack.11, align 16)
+; MIR64-DAG: STFD killed $f21, 312, $x1 :: (store (s64) into %fixed-stack.10)
+; MIR64-DAG: STFD killed $f22, 320, $x1 :: (store (s64) into %fixed-stack.9, align 16)
+; MIR64-DAG: STFD killed $f23, 328, $x1 :: (store (s64) into %fixed-stack.8)
+; MIR64-DAG: STFD killed $f24, 336, $x1 :: (store (s64) into %fixed-stack.7, align 16)
+; MIR64-DAG: STFD killed $f25, 344, $x1 :: (store (s64) into %fixed-stack.6)
+; MIR64-DAG: STFD killed $f26, 352, $x1 :: (store (s64) into %fixed-stack.5, align 16)
+; MIR64-DAG: STFD killed $f27, 360, $x1 :: (store (s64) into %fixed-stack.4)
+; MIR64-DAG: STFD killed $f28, 368, $x1 :: (store (s64) into %fixed-stack.3, align 16)
+; MIR64-DAG: STFD killed $f29, 376, $x1 :: (store (s64) into %fixed-stack.2)
+; MIR64-DAG: STFD killed $f30, 384, $x1 :: (store (s64) into %fixed-stack.1, align 16)
; MIR64-DAG: STFD killed $f31, 392, $x1 :: (store (s64) into %fixed-stack.0)
; MIR64: INLINEASM
; MIR64-NEXT: BL8_NOP
+
; MIR64-DAG: $f31 = LFD 392, $x1 :: (load (s64) from %fixed-stack.0)
-; MIR64-DAG: $f21 = LFD 312, $x1 :: (load (s64) from %fixed-stack.1)
-; MIR64-DAG: $f19 = LFD 296, $x1 :: (load (s64) from %fixed-stack.2)
-; MIR64-DAG: $f14 = LFD 256, $x1 :: (load (s64) from %fixed-stack.3, align 16)
-; MIR64-DAG: $x31 = LD 248, $x1 :: (load (s64) from %fixed-stack.4)
-; MIR64-DAG: $x25 = LD 200, $x1 :: (load (s64) from %fixed-stack.5)
-; MIR64-DAG: $x14 = LD 112, $x1 :: (load (s64) from %fixed-stack.6, align 16)
+; MIR64-DAG: $f30 = LFD 384, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+; MIR64-DAG: $f29 = LFD 376, $x1 :: (load (s64) from %fixed-stack.2)
+; MIR64-DAG: $f28 = LFD 368, $x1 :: (load (s64) from %fixed-stack.3, align 16)
+; MIR64-DAG: $f27 = LFD 360, $x1 :: (load (s64) from %fixed-stack.4)
+; MIR64-DAG: $f26 = LFD 352, $x1 :: (load (s64) from %fixed-stack.5, align 16)
+; MIR64-DAG: $f25 = LFD 344, $x1 :: (load (s64) from %fixed-stack.6)
+; MIR64-DAG: $f24 = LFD 336, $x1 :: (load (s64) from %fixed-stack.7, align 16)
+; MIR64-DAG: $f23 = LFD 328, $x1 :: (load (s64) from %fixed-stack.8)
+; MIR64-DAG: $f22 = LFD 320, $x1 :: (load (s64) from %fixed-stack.9, align 16)
+; MIR64-DAG: $f21 = LFD 312, $x1 :: (load (s64) from %fixed-stack.10)
+; MIR64-DAG: $f20 = LFD 304, $x1 :: (load (s64) from %fixed-stack.11, align 16)
+; MIR64-DAG: $f19 = LFD 296, $x1 :: (load (s64) from %fixed-stack.12)
+; MIR64-DAG: $f18 = LFD 288, $x1 :: (load (s64) from %fixed-stack.13, align 16)
+; MIR64-DAG: $f17 = LFD 280, $x1 :: (load (s64) from %fixed-stack.14)
+; MIR64-DAG: $f16 = LFD 272, $x1 :: (load (s64) from %fixed-stack.15, align 16)
+; MIR64-DAG: $f15 = LFD 264, $x1 :: (load (s64) from %fixed-stack.16)
+; MIR64-DAG: $f14 = LFD 256, $x1 :: (load (s64) from %fixed-stack.17, align 16)
+; MIR64-DAG: $x31 = LD 248, $x1 :: (load (s64) from %fixed-stack.18)
+; MIR64-DAG: $x30 = LD 240, $x1 :: (load (s64) from %fixed-stack.19, align 16)
+; MIR64-DAG: $x29 = LD 232, $x1 :: (load (s64) from %fixed-stack.20)
+; MIR64-DAG: $x28 = LD 224, $x1 :: (load (s64) from %fixed-stack.21, align 16)
+; MIR64-DAG: $x27 = LD 216, $x1 :: (load (s64) from %fixed-stack.22)
+; MIR64-DAG: $x26 = LD 208, $x1 :: (load (s64) from %fixed-stack.23, align 16)
+; MIR64-DAG: $x25 = LD 200, $x1 :: (load (s64) from %fixed-stack.24)
+; MIR64-DAG: $x24 = LD 192, $x1 :: (load (s64) from %fixed-stack.25, align 16)
+; MIR64-DAG: $x23 = LD 184, $x1 :: (load (s64) from %fixed-stack.26)
+; MIR64-DAG: $x22 = LD 176, $x1 :: (load (s64) from %fixed-stack.27, align 16)
+; MIR64-DAG: $x21 = LD 168, $x1 :: (load (s64) from %fixed-stack.28)
+; MIR64-DAG: $x20 = LD 160, $x1 :: (load (s64) from %fixed-stack.29, align 16)
+; MIR64-DAG: $x19 = LD 152, $x1 :: (load (s64) from %fixed-stack.30)
+; MIR64-DAG: $x18 = LD 144, $x1 :: (load (s64) from %fixed-stack.31, align 16)
+; MIR64-DAG: $x17 = LD 136, $x1 :: (load (s64) from %fixed-stack.32)
+; MIR64-DAG: $x16 = LD 128, $x1 :: (load (s64) from %fixed-stack.33, align 16)
+; MIR64-DAG: $x15 = LD 120, $x1 :: (load (s64) from %fixed-stack.34)
+; MIR64-DAG: $x14 = LD 112, $x1 :: (load (s64) from %fixed-stack.35, align 16)
+
; MIR64: $x1 = ADDI8 $x1, 400
; MIR64-NEXT: $x0 = LD 16, $x1
; MIR64-NEXT: MTLR8 $x0, implicit-def $lr8
; MIR64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
-
-; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31
+; MIR32: liveins: $r3, $r13, $r14, $r15, $r16, $r17, $r18, $r19, $r20, $r21, $r22, $r23, $r24, $r25, $r26, $r27, $r28, $r29, $r30, $r31, $f14, $f15, $f16, $f17, $f18, $f19, $f20, $f21, $f22, $f23, $f24, $f25, $f26, $f27, $f28, $f29, $f30, $f31
; MIR32: $r0 = MFLR implicit $lr
; MIR32-NEXT: $r1 = STWU $r1, -288, $r1
; MIR32-NEXT: STW killed $r0, 296, $r1
-; MIR32-DAG: STW killed $r13, 68, $r1 :: (store (s32) into %fixed-stack.7)
-; MIR32-DAG: STW killed $r14, 72, $r1 :: (store (s32) into %fixed-stack.6, align 8)
-; MIR32-DAG: STW killed $r25, 116, $r1 :: (store (s32) into %fixed-stack.5)
-; MIR32-DAG: STW killed $r31, 140, $r1 :: (store (s32) into %fixed-stack.4)
-; MIR32-DAG: STFD killed $f14, 144, $r1 :: (store (s64) into %fixed-stack.3, align 16)
-; MIR32-DAG: STFD killed $f19, 184, $r1 :: (store (s64) into %fixed-stack.2)
-; MIR32-DAG: STFD killed $f21, 200, $r1 :: (store (s64) into %fixed-stack.1)
+; MIR32-DAG: STW killed $r13, 68, $r1 :: (store (s32) into %fixed-stack.36)
+; MIR32-DAG: STW killed $r14, 72, $r1 :: (store (s32) into %fixed-stack.35, align 8)
+; MIR32-DAG: STW killed $r15, 76, $r1 :: (store (s32) into %fixed-stack.34)
+; MIR32-DAG: STW killed $r16, 80, $r1 :: (store (s32) into %fixed-stack.33, align 16)
+; MIR32-DAG: STW killed $r17, 84, $r1 :: (store (s32) into %fixed-stack.32)
+; MIR32-DAG: STW killed $r18, 88, $r1 :: (store (s32) into %fixed-stack.31, align 8)
+; MIR32-DAG: STW killed $r19, 92, $r1 :: (store (s32) into %fixed-stack.30)
+; MIR32-DAG: STW killed $r20, 96, $r1 :: (store (s32) into %fixed-stack.29, align 16)
+; MIR32-DAG: STW killed $r21, 100, $r1 :: (store (s32) into %fixed-stack.28)
+; MIR32-DAG: STW killed $r22, 104, $r1 :: (store (s32) into %fixed-stack.27, align 8)
+; MIR32-DAG: STW killed $r23, 108, $r1 :: (store (s32) into %fixed-stack.26)
+; MIR32-DAG: STW killed $r24, 112, $r1 :: (store (s32) into %fixed-stack.25, align 16)
+; MIR32-DAG: STW killed $r25, 116, $r1 :: (store (s32) into %fixed-stack.24)
+; MIR32-DAG: STW killed $r26, 120, $r1 :: (store (s32) into %fixed-stack.23, align 8)
+; MIR32-DAG: STW killed $r27, 124, $r1 :: (store (s32) into %fixed-stack.22)
+; MIR32-DAG: STW killed $r28, 128, $r1 :: (store (s32) into %fixed-stack.21, align 16)
+; MIR32-DAG: STW killed $r29, 132, $r1 :: (store (s32) into %fixed-stack.20)
+; MIR32-DAG: STW killed $r30, 136, $r1 :: (store (s32) into %fixed-stack.19, align 8)
+; MIR32-DAG: STW killed $r31, 140, $r1 :: (store (s32) into %fixed-stack.18)
+; MIR32-DAG: STFD killed $f14, 144, $r1 :: (store (s64) into %fixed-stack.17, align 16)
+; MIR32-DAG: STFD killed $f15, 152, $r1 :: (store (s64) into %fixed-stack.16)
+; MIR32-DAG: STFD killed $f16, 160, $r1 :: (store (s64) into %fixed-stack.15, align 16)
+; MIR32-DAG: STFD killed $f17, 168, $r1 :: (store (s64) into %fixed-stack.14)
+; MIR32-DAG: STFD killed $f18, 176, $r1 :: (store (s64) into %fixed-stack.13, align 16)
+; MIR32-DAG: STFD killed $f19, 184, $r1 :: (store (s64) into %fixed-stack.12)
+; MIR32-DAG: STFD killed $f20, 192, $r1 :: (store (s64) into %fixed-stack.11, align 16)
+; MIR32-DAG: STFD killed $f21, 200, $r1 :: (store (s64) into %fixed-stack.10)
+; MIR32-DAG: STFD killed $f22, 208, $r1 :: (store (s64) into %fixed-stack.9, align 16)
+; MIR32-DAG: STFD killed $f23, 216, $r1 :: (store (s64) into %fixed-stack.8)
+; MIR32-DAG: STFD killed $f24, 224, $r1 :: (store (s64) into %fixed-stack.7, align 16)
+; MIR32-DAG: STFD killed $f25, 232, $r1 :: (store (s64) into %fixed-stack.6)
+; MIR32-DAG: STFD killed $f26, 240, $r1 :: (store (s64) into %fixed-stack.5, align 16)
+; MIR32-DAG: STFD killed $f27, 248, $r1 :: (store (s64) into %fixed-stack.4)
+; MIR32-DAG: STFD killed $f28, 256, $r1 :: (store (s64) into %fixed-stack.3, align 16)
+; MIR32-DAG: STFD killed $f29, 264, $r1 :: (store (s64) into %fixed-stack.2)
+; MIR32-DAG: STFD killed $f30, 272, $r1 :: (store (s64) into %fixed-stack.1, align 16)
; MIR32-DAG: STFD killed $f31, 280, $r1 :: (store (s64) into %fixed-stack.0)
; MIR32: INLINEASM
; MIR32: BL_NOP
; MIR32-DAG: $f31 = LFD 280, $r1 :: (load (s64) from %fixed-stack.0)
-; MIR32-DAG: $f21 = LFD 200, $r1 :: (load (s64) from %fixed-stack.1)
-; MIR32-DAG: $f19 = LFD 184, $r1 :: (load (s64) from %fixed-stack.2)
-; MIR32-DAG: $f14 = LFD 144, $r1 :: (load (s64) from %fixed-stack.3, align 16)
-; MIR32-DAG: $r31 = LWZ 140, $r1 :: (load (s32) from %fixed-stack.4)
-; MIR32-DAG: $r25 = LWZ 116, $r1 :: (load (s32) from %fixed-stack.5)
-; MIR32-DAG: $r14 = LWZ 72, $r1 :: (load (s32) from %fixed-stack.6, align 8)
-; MIR32-DAG: $r13 = LWZ 68, $r1 :: (load (s32) from %fixed-stack.7)
+; MIR32-DAG: $f30 = LFD 272, $r1 :: (load (s64) from %fixed-stack.1, align 16)
+; MIR32-DAG: $f29 = LFD 264, $r1 :: (load (s64) from %fixed-stack.2)
+; MIR32-DAG: $f28 = LFD 256, $r1 :: (load (s64) from %fixed-stack.3, align 16)
+; MIR32-DAG: $f27 = LFD 248, $r1 :: (load (s64) from %fixed-stack.4)
+; MIR32-DAG: $f26 = LFD 240, $r1 :: (load (s64) from %fixed-stack.5, align 16)
+; MIR32-DAG: $f25 = LFD 232, $r1 :: (load (s64) from %fixed-stack.6)
+; MIR32-DAG: $f24 = LFD 224, $r1 :: (load (s64) from %fixed-stack.7, align 16)
+; MIR32-DAG: $f23 = LFD 216, $r1 :: (load (s64) from %fixed-stack.8)
+; MIR32-DAG: $f22 = LFD 208, $r1 :: (load (s64) from %fixed-stack.9, align 16)
+; MIR32-DAG: $f21 = LFD 200, $r1 :: (load (s64) from %fixed-stack.10)
+; MIR32-DAG: $f20 = LFD 192, $r1 :: (load (s64) from %fixed-stack.11, align 16)
+; MIR32-DAG: $f19 = LFD 184, $r1 :: (load (s64) from %fixed-stack.12)
+; MIR32-DAG: $f18 = LFD 176, $r1 :: (load (s64) from %fixed-stack.13, align 16)
+; MIR32-DAG: $f17 = LFD 168, $r1 :: (load (s64) from %fixed-stack.14)
+; MIR32-DAG: $f16 = LFD 160, $r1 :: (load (s64) from %fixed-stack.15, align 16)
+; MIR32-DAG: $f15 = LFD 152, $r1 :: (load (s64) from %fixed-stack.16)
+; MIR32-DAG: $f14 = LFD 144, $r1 :: (load (s64) from %fixed-stack.17, align 16)
+; MIR32-DAG: $r31 = LWZ 140, $r1 :: (load (s32) from %fixed-stack.18)
+; MIR32-DAG: $r30 = LWZ 136, $r1 :: (load (s32) from %fixed-stack.19, align 8)
+; MIR32-DAG: $r29 = LWZ 132, $r1 :: (load (s32) from %fixed-stack.20)
+; MIR32-DAG: $r28 = LWZ 128, $r1 :: (load (s32) from %fixed-stack.21, align 16)
+; MIR32-DAG: $r27 = LWZ 124, $r1 :: (load (s32) from %fixed-stack.22)
+; MIR32-DAG: $r26 = LWZ 120, $r1 :: (load (s32) from %fixed-stack.23, align 8)
+; MIR32-DAG: $r25 = LWZ 116, $r1 :: (load (s32) from %fixed-stack.24)
+; MIR32-DAG: $r24 = LWZ 112, $r1 :: (load (s32) from %fixed-stack.25, align 16)
+; MIR32-DAG: $r23 = LWZ 108, $r1 :: (load (s32) from %fixed-stack.26)
+; MIR32-DAG: $r22 = LWZ 104, $r1 :: (load (s32) from %fixed-stack.27, align 8)
+; MIR32-DAG: $r21 = LWZ 100, $r1 :: (load (s32) from %fixed-stack.28)
+; MIR32-DAG: $r20 = LWZ 96, $r1 :: (load (s32) from %fixed-stack.29, align 16)
+; MIR32-DAG: $r19 = LWZ 92, $r1 :: (load (s32) from %fixed-stack.30)
+; MIR32-DAG: $r18 = LWZ 88, $r1 :: (load (s32) from %fixed-stack.31, align 8)
+; MIR32-DAG: $r17 = LWZ 84, $r1 :: (load (s32) from %fixed-stack.32)
+; MIR32-DAG: $r16 = LWZ 80, $r1 :: (load (s32) from %fixed-stack.33, align 16)
+; MIR32-DAG: $r15 = LWZ 76, $r1 :: (load (s32) from %fixed-stack.34)
+; MIR32-DAG: $r14 = LWZ 72, $r1 :: (load (s32) from %fixed-stack.35, align 8)
+; MIR32-DAG: $r13 = LWZ 68, $r1 :: (load (s32) from %fixed-stack.36)
; MIR32: $r1 = ADDI $r1, 288
; MIR32-NEXT: $r0 = LWZ 8, $r1
; MIR32-NEXT: MTLR $r0, implicit-def $lr
@@ -219,23 +693,81 @@ define dso_local double @fprs_and_gprs(i32 signext %i) {
; ASM64: mflr 0
; ASM64-NEXT: stdu 1, -400(1)
; ASM64-NEXT: std 0, 416(1)
-; ASM64-DAG: std 14, 112(1) # 8-byte Folded Spill
-; ASM64-DAG: std 25, 200(1) # 8-byte Folded Spill
-; ASM64-DAG: std 31, 248(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 14, 256(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 19, 296(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 21, 312(1) # 8-byte Folded Spill
-; ASM64-DAG: stfd 31, 392(1) # 8-byte Folded Spill
+; ASM64-DAG: std 14, 112(1) # 8-byte Folded Spill
+; ASM64-DAG: std 15, 120(1) # 8-byte Folded Spill
+; ASM64-DAG: std 16, 128(1) # 8-byte Folded Spill
+; ASM64-DAG: std 17, 136(1) # 8-byte Folded Spill
+; ASM64-DAG: std 18, 144(1) # 8-byte Folded Spill
+; ASM64-DAG: std 19, 152(1) # 8-byte Folded Spill
+; ASM64-DAG: std 20, 160(1) # 8-byte Folded Spill
+; ASM64-DAG: std 21, 168(1) # 8-byte Folded Spill
+; ASM64-DAG: std 22, 176(1) # 8-byte Folded Spill
+; ASM64-DAG: std 23, 184(1) # 8-byte Folded Spill
+; ASM64-DAG: std 24, 192(1) # 8-byte Folded Spill
+; ASM64-DAG: std 25, 200(1) # 8-byte Folded Spill
+; ASM64-DAG: std 26, 208(1) # 8-byte Folded Spill
+; ASM64-DAG: std 27, 216(1) # 8-byte Folded Spill
+; ASM64-DAG: std 28, 224(1) # 8-byte Folded Spill
+; ASM64-DAG: std 29, 232(1) # 8-byte Folded Spill
+; ASM64-DAG: std 30, 240(1) # 8-byte Folded Spill
+; ASM64-DAG: std 31, 248(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 14, 256(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 15, 264(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 16, 272(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 17, 280(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 18, 288(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 19, 296(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 20, 304(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 21, 312(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 22, 320(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 23, 328(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 24, 336(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 25, 344(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 26, 352(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 27, 360(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 28, 368(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 29, 376(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 30, 384(1) # 8-byte Folded Spill
+; ASM64-DAG: stfd 31, 392(1) # 8-byte Folded Spill
; ASM64: bl .dummy
+; ASM64-DAG: lfd 31, 392(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 30, 384(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 29, 376(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 28, 368(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 27, 360(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 26, 352(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 25, 344(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 24, 336(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 23, 328(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 22, 320(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 21, 312(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 20, 304(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 19, 296(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 18, 288(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 17, 280(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 16, 272(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 15, 264(1) # 8-byte Folded Reload
+; ASM64-DAG: lfd 14, 256(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 31, 248(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 30, 240(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 29, 232(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 28, 224(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 27, 216(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 26, 208(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 25, 200(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 24, 192(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 23, 184(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 22, 176(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 21, 168(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 20, 160(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 19, 152(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 18, 144(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 17, 136(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 16, 128(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 15, 120(1) # 8-byte Folded Reload
+; ASM64-DAG: ld 14, 112(1) # 8-byte Folded Reload
-; ASM64-DAG: lfd 31, 392(1) # 8-byte Folded Reload
-; ASM64-DAG: lfd 21, 312(1) # 8-byte Folded Reload
-; ASM64-DAG: lfd 19, 296(1) # 8-byte Folded Reload
-; ASM64-DAG: lfd 14, 256(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 31, 248(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 25, 200(1) # 8-byte Folded Reload
-; ASM64-DAG: ld 14, 112(1) # 8-byte Folded Reload
; ASM64: addi 1, 1, 400
; ASM64-NEXT: ld 0, 16(1)
; ASM64-NEXT: mtlr 0
diff --git a/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll b/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
new file mode 100644
index 00000000000000..56c9bc0c04bbac
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
@@ -0,0 +1,300 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs --vec-extabi \
+; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s --check-prefix 32BIT
+
+; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs --vec-extabi \
+; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix 64BIT
+
+ at _ZTIi = external constant i8*
+
+; Function Attrs: uwtable mustprogress
+define dso_local signext i32 @_Z5test2iPPKc(i32 signext %argc, i8** nocapture readnone %argv) local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; 32BIT-LABEL: _Z5test2iPPKc:
+; 32BIT: # %bb.0: # %entry
+; 32BIT-NEXT: mflr 0
+; 32BIT-NEXT: stwu 1, -464(1)
+; 32BIT-NEXT: stw 0, 472(1)
+; 32BIT-NEXT: stw 30, 320(1) # 4-byte Folded Spill
+; 32BIT-NEXT: li 30, 0
+; 32BIT-NEXT: stxv 52, 64(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stxv 53, 80(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 31, 324(1) # 4-byte Folded Spill
+; 32BIT-NEXT: mr 31, 3
+; 32BIT-NEXT: stw 14, 256(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 54, 96(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 15, 260(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 55, 112(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 16, 264(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 56, 128(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 17, 268(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw 18, 272(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 57, 144(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 19, 276(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 58, 160(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 20, 280(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 59, 176(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 21, 284(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw 22, 288(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 60, 192(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 23, 292(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 61, 208(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 24, 296(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 62, 224(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 25, 300(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw 26, 304(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv 63, 240(1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw 27, 308(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw 28, 312(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw 29, 316(1) # 4-byte Folded Spill
+; 32BIT-NEXT: stfd 15, 328(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 16, 336(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 17, 344(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 18, 352(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 19, 360(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 20, 368(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 21, 376(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 22, 384(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 23, 392(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 24, 400(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 25, 408(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 26, 416(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
+; 32BIT-NEXT: #APP
+; 32BIT-NEXT: nop
+; 32BIT-NEXT: #NO_APP
+; 32BIT-NEXT: L..tmp0:
+; 32BIT-NEXT: bl ._Z4testi[PR]
+; 32BIT-NEXT: nop
+; 32BIT-NEXT: L..tmp1:
+; 32BIT-NEXT: L..BB0_1: # %return
+; 32BIT-NEXT: lxv 63, 240(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 62, 224(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 61, 208(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 60, 192(1) # 16-byte Folded Reload
+; 32BIT-NEXT: mr 3, 30
+; 32BIT-NEXT: lxv 59, 176(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 58, 160(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 57, 144(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 56, 128(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 55, 112(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 54, 96(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 53, 80(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv 52, 64(1) # 16-byte Folded Reload
+; 32BIT-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz 31, 324(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 30, 320(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 29, 316(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz 28, 312(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 27, 308(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 26, 304(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd 26, 416(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz 25, 300(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 24, 296(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 23, 292(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd 25, 408(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz 22, 288(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 21, 284(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 20, 280(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd 24, 400(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz 19, 276(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 18, 272(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 17, 268(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd 23, 392(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz 16, 264(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 15, 260(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz 14, 256(1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd 22, 384(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 21, 376(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 20, 368(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 19, 360(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 18, 352(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 17, 344(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 16, 336(1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd 15, 328(1) # 8-byte Folded Reload
+; 32BIT-NEXT: addi 1, 1, 464
+; 32BIT-NEXT: lwz 0, 8(1)
+; 32BIT-NEXT: mtlr 0
+; 32BIT-NEXT: blr
+; 32BIT-NEXT: L..BB0_2: # %lpad
+; 32BIT-NEXT: L..tmp2:
+; 32BIT-NEXT: bl .__cxa_begin_catch[PR]
+; 32BIT-NEXT: nop
+; 32BIT-NEXT: lwz 3, 0(3)
+; 32BIT-NEXT: add 30, 3, 31
+; 32BIT-NEXT: bl .__cxa_end_catch[PR]
+; 32BIT-NEXT: nop
+; 32BIT-NEXT: b L..BB0_1
+;
+; 64BIT-LABEL: _Z5test2iPPKc:
+; 64BIT: # %bb.0: # %entry
+; 64BIT-NEXT: mflr 0
+; 64BIT-NEXT: stdu 1, -592(1)
+; 64BIT-NEXT: std 0, 608(1)
+; 64BIT-NEXT: std 30, 440(1) # 8-byte Folded Spill
+; 64BIT-NEXT: li 30, 0
+; 64BIT-NEXT: stxv 52, 112(1) # 16-byte Folded Spill
+; 64BIT-NEXT: stxv 53, 128(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 31, 448(1) # 8-byte Folded Spill
+; 64BIT-NEXT: mr 31, 3
+; 64BIT-NEXT: std 14, 312(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 54, 144(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 15, 320(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 55, 160(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 16, 328(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 56, 176(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 17, 336(1) # 8-byte Folded Spill
+; 64BIT-NEXT: std 18, 344(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 57, 192(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 19, 352(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 58, 208(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 20, 360(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 59, 224(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 21, 368(1) # 8-byte Folded Spill
+; 64BIT-NEXT: std 22, 376(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 60, 240(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 23, 384(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 61, 256(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 24, 392(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 62, 272(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 25, 400(1) # 8-byte Folded Spill
+; 64BIT-NEXT: std 26, 408(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv 63, 288(1) # 16-byte Folded Spill
+; 64BIT-NEXT: std 27, 416(1) # 8-byte Folded Spill
+; 64BIT-NEXT: std 28, 424(1) # 8-byte Folded Spill
+; 64BIT-NEXT: std 29, 432(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 15, 456(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 16, 464(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 17, 472(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 18, 480(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 19, 488(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 20, 496(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 21, 504(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 22, 512(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 23, 520(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 24, 528(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 25, 536(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 26, 544(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 27, 552(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 28, 560(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 29, 568(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 30, 576(1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd 31, 584(1) # 8-byte Folded Spill
+; 64BIT-NEXT: #APP
+; 64BIT-NEXT: nop
+; 64BIT-NEXT: #NO_APP
+; 64BIT-NEXT: L..tmp0:
+; 64BIT-NEXT: bl ._Z4testi[PR]
+; 64BIT-NEXT: nop
+; 64BIT-NEXT: L..tmp1:
+; 64BIT-NEXT: L..BB0_1: # %return
+; 64BIT-NEXT: lxv 63, 288(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 62, 272(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 61, 256(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 60, 240(1) # 16-byte Folded Reload
+; 64BIT-NEXT: extsw 3, 30
+; 64BIT-NEXT: lxv 59, 224(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 58, 208(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 57, 192(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 56, 176(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 55, 160(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 54, 144(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 53, 128(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv 52, 112(1) # 16-byte Folded Reload
+; 64BIT-NEXT: lfd 31, 584(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 30, 576(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 29, 568(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 28, 560(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 31, 448(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 30, 440(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 29, 432(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 27, 552(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 28, 424(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 27, 416(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 26, 408(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 26, 544(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 25, 400(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 24, 392(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 23, 384(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 25, 536(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 22, 376(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 21, 368(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 20, 360(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 24, 528(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 19, 352(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 18, 344(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 17, 336(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 23, 520(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 16, 328(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 15, 320(1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld 14, 312(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 22, 512(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 21, 504(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 20, 496(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 19, 488(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 18, 480(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 17, 472(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 16, 464(1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd 15, 456(1) # 8-byte Folded Reload
+; 64BIT-NEXT: addi 1, 1, 592
+; 64BIT-NEXT: ld 0, 16(1)
+; 64BIT-NEXT: mtlr 0
+; 64BIT-NEXT: blr
+; 64BIT-NEXT: L..BB0_2: # %lpad
+; 64BIT-NEXT: L..tmp2:
+; 64BIT-NEXT: bl .__cxa_begin_catch[PR]
+; 64BIT-NEXT: nop
+; 64BIT-NEXT: lwz 3, 0(3)
+; 64BIT-NEXT: add 30, 3, 31
+; 64BIT-NEXT: bl .__cxa_end_catch[PR]
+; 64BIT-NEXT: nop
+; 64BIT-NEXT: b L..BB0_1
+entry:
+ tail call void asm sideeffect "nop", "~{r14},~{f15},~{v20}"()
+ %call = invoke signext i32 @_Z4testi(i32 signext %argc)
+ to label %return unwind label %lpad
+
+lpad: ; preds = %entry
+ %0 = landingpad { i8*, i32 }
+ catch i8* bitcast (i8** @_ZTIi to i8*)
+ %1 = extractvalue { i8*, i32 } %0, 1
+ %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #3
+ %matches = icmp eq i32 %1, %2
+ br i1 %matches, label %catch, label %eh.resume
+
+catch: ; preds = %lpad
+ %3 = extractvalue { i8*, i32 } %0, 0
+ %4 = tail call i8* @__cxa_begin_catch(i8* %3) #3
+ %5 = bitcast i8* %4 to i32*
+ %6 = load i32, i32* %5, align 4
+ %add = add nsw i32 %6, %argc
+ tail call void @__cxa_end_catch()
+ br label %return
+
+return: ; preds = %entry, %catch
+ %retval.0 = phi i32 [ %add, %catch ], [ 0, %entry ]
+ ret i32 %retval.0
+
+eh.resume: ; preds = %lpad
+ resume { i8*, i32 } %0
+}
+
+declare signext i32 @_Z4testi(i32 signext) local_unnamed_addr
+
+declare i32 @__gxx_personality_v0(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*)
+
+declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr
+
+declare void @__cxa_end_catch() local_unnamed_addr
+
+attributes #0 = { uwtable }
diff --git a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
index cf51f79c7e9893..4a37372a6017c8 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
@@ -18,23 +18,33 @@ body: |
BLR implicit $lr, implicit $rm, implicit $r3
; CHECK-LABEL: fixedStack:
- ; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default,
+ ; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default,
+ ; CHECK-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+ ; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
+ ; CHECK-NEXT: - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 8, stack-id: default,
+ ; CHECK-NEXT: callee-saved-register: '$r30', callee-saved-restored: true, debug-info-variable: '',
+ ; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
+ ; CHECK-NEXT: - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default,
; CHECK-NEXT: callee-saved-register: '$r29', callee-saved-restored: true, debug-info-variable: '',
; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
- ; CHECK-NEXT: - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+ ; CHECK-NEXT: - { id: 3, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
; CHECK-NEXT: debug-info-location: '' }
; CHECK-LABEL: stack:
; CHECK: bb.0.entry:
- ; CHECK-NEXT: liveins: $r3, $r29, $cr2, $cr4
+ ; CHECK-NEXT: liveins: $r3, $r29, $r30, $r31, $cr2, $cr4
; CHECK: $r12 = MFCR implicit killed $cr2, implicit killed $cr4
; CHECK-NEXT: STW killed $r12, 4, $r1
- ; CHECK-NEXT: STW killed $r29, -12, $r1 :: (store (s32) into %fixed-stack.0)
+ ; CHECK-NEXT: STW killed $r29, -12, $r1 :: (store (s32) into %fixed-stack.2)
+ ; CHECK-NEXT: STW killed $r30, -8, $r1 :: (store (s32) into %fixed-stack.1, align 8)
+ ; CHECK-NEXT: STW killed $r31, -4, $r1 :: (store (s32) into %fixed-stack.0)
- ; CHECK: $r29 = LWZ -12, $r1 :: (load (s32) from %fixed-stack.0)
+ ; CHECK: $r31 = LWZ -4, $r1 :: (load (s32) from %fixed-stack.0)
+ ; CHECK-NEXT: $r30 = LWZ -8, $r1 :: (load (s32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: $r29 = LWZ -12, $r1 :: (load (s32) from %fixed-stack.2)
; CHECK-NEXT: $r12 = LWZ 4, $r1
; CHECK-NEXT: $cr2 = MTOCRF $r12
; CHECK-NEXT: $cr4 = MTOCRF killed $r12
@@ -49,14 +59,14 @@ liveins:
body: |
bb.0.entry:
liveins: $r3
- renamable $r14 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ renamable $r31 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr3lt = COPY $cr0gt
- renamable $r3 = COPY $r14
+ renamable $r3 = COPY $r31
BLR implicit $lr, implicit $rm, implicit $r3
; CHECK-LABEL: fixedStack:
- ; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -72, size: 4, alignment: 8, stack-id: default,
- ; CHECK-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
+ ; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default,
+ ; CHECK-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
; CHECK-NEXT: - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr3',
@@ -65,12 +75,12 @@ body: |
; CHECK-LABEL: stack:
; CHECK: bb.0.entry:
- ; CHECK-NEXT: liveins: $r3, $r14, $cr3
+ ; CHECK-NEXT: liveins: $r3, $r31, $cr3
; CHECK: $r12 = MFCR implicit killed $cr3
; CHECK-NEXT: STW killed $r12, 4, $r1
- ; CHECK-NEXT: STW killed $r14, -72, $r1 :: (store (s32) into %fixed-stack.0, align 8)
+ ; CHECK-NEXT: STW killed $r31, -4, $r1 :: (store (s32) into %fixed-stack.0)
- ; CHECK: $r14 = LWZ -72, $r1 :: (load (s32) from %fixed-stack.0, align 8)
+ ; CHECK: $r31 = LWZ -4, $r1 :: (load (s32) from %fixed-stack.0)
; CHECK-NEXT: $r12 = LWZ 4, $r1
; CHECK-NEXT: $cr3 = MTOCRF killed $r12
diff --git a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
index f22aeffdbb466a..32368a79fed18e 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
@@ -31,7 +31,7 @@
; After the prologue is set.
; DISABLE: cmpw 3, 4
; DISABLE-32: stw 0,
-; DISABLE-64-AIX: std 0,
+; DISABLE-64: std 0,
; DISABLE-NEXT: bge 0, {{.*}}[[EXIT_LABEL:BB[0-9_]+]]
;
; Store %a on the stack
@@ -57,7 +57,7 @@
; DISABLE-NEXT: blr
;
-define i32 @foo(i32 %a, i32 %b) {
+define i32 @foo(i32 %a, i32 %b) #0 {
%tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false
@@ -187,7 +187,7 @@ declare i32 @something(...)
; CHECK: %for.exit
; CHECK: mtlr {{[0-9]+}}
; CHECK: blr
-define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
+define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) #0 {
entry:
br label %for.preheader
@@ -276,7 +276,7 @@ for.end: ; preds = %for.body
; Shift second argument by one and store into returned register.
; ENABLE: slwi 3, 4, 1
; ENABLE-NEXT: blr
-define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
+define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
entry:
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader
@@ -421,14 +421,14 @@ entry:
; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
;
; Prologue code.
-; Make sure we save the CSR used in the inline asm: r14
+; Make sure we save the CSR used in the inline asm: r31
; ENABLE-DAG: li [[IV:[0-9]+]], 10
-; ENABLE-64-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
-; ENABLE-32-DAG: stw 14, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill
+; ENABLE-64-DAG: std 31, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
+; ENABLE-32-DAG: stw 31, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill
;
; DISABLE: cmplwi 3, 0
-; DISABLE-64-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
-; DISABLE-32-NEXT: stw 14, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill
+; DISABLE-64-NEXT: std 31, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
+; DISABLE-32-NEXT: stw 31, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill
; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
; DISABLE: li [[IV:[0-9]+]], 10
;
@@ -437,22 +437,22 @@ entry:
;
; CHECK: {{.*}}[[LOOP_LABEL:BB[0-9_]+]]: # %for.body
; Inline asm statement.
-; CHECK: addi 14, 14, 1
+; CHECK: addi 31, 14, 1
; CHECK: bdnz {{.*}}[[LOOP_LABEL]]
;
; Epilogue code.
; CHECK: li 3, 0
-; CHECK-64-DAG: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
-; CHECK-32-DAG: lwz 14, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
+; CHECK-64-DAG: ld 31, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
+; CHECK-32-DAG: lwz 31, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
; CHECK-DAG: nop
; CHECK: blr
;
; CHECK: [[ELSE_LABEL]]
; CHECK-NEXT: slwi 3, 4, 1
-; DISABLE-64-NEXT: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
-; DISABLE-32-NEXT: lwz 14, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
+; DISABLE-64-NEXT: ld 31, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
+; DISABLE-32-NEXT: lwz 31, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
; CHECK-NEXT: blr
-define i32 @inlineAsm(i32 %cond, i32 %N) {
+define i32 @inlineAsm(i32 %cond, i32 %N) #0 {
entry:
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader
@@ -463,7 +463,7 @@ for.preheader:
for.body: ; preds = %entry, %for.body
%i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
- tail call void asm "addi 14, 14, 1", "~{r14}"()
+ tail call void asm "addi 31, 14, 1", "~{r31}"()
%inc = add nuw nsw i32 %i.03, 1
%exitcond = icmp eq i32 %inc, 10
br i1 %exitcond, label %for.exit, label %for.body
@@ -698,7 +698,7 @@ end:
; Ensure no subsequent uses of callee-save register before end of function
; CHECKXX-NOT: {{[a-z]+}} [[CSR]]
; CHECK: blr
-define signext i32 @transpose() {
+define signext i32 @transpose() #0 {
entry:
%0 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 1), align 4
%shl.i = shl i32 %0, 7
@@ -843,3 +843,5 @@ if.end.6:
%cmp1.7 = icmp eq i32 %18, %conv18.i
br i1 %cmp1.7, label %if.then, label %cleanup
}
+
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
index f4af2ad21a5675..9d00db269e33fc 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -1,15 +1,16 @@
-# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-altivec \
+# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
+# RUN: FileCheck %s --check-prefixes=SAVEONE
-# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
+# RUN: llc -mtriple powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-altivec \
+# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
+# RUN: FileCheck %s --check-prefixes=SAVEALL
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
+# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
+# RUN: FileCheck %s --check-prefixes=SAVEALL-AIX
---
name: CRAllSave
@@ -20,6 +21,52 @@ liveins:
body: |
bb.0.entry:
liveins: $x3
+ ; SAVEONE-LABEL: name: CRAllSave
+ ; SAVEONE: liveins: $x3, $x29, $cr2, $cr4
+ ; SAVEONE: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
+ ; SAVEONE: STW8 killed $x12, 8, $x1
+ ; SAVEONE: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEONE: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEONE: renamable $cr2lt = COPY $cr0gt
+ ; SAVEONE: renamable $cr4lt = COPY $cr0gt
+ ; SAVEONE: renamable $x3 = COPY $x29
+ ; SAVEONE: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEONE: $x12 = LWZ8 8, $x1
+ ; SAVEONE: $cr2 = MTOCRF8 $x12
+ ; SAVEONE: $cr4 = MTOCRF8 killed $x12
+ ; SAVEONE: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-LABEL: name: CRAllSave
+ ; SAVEALL: liveins: $x3, $x29, $cr2, $cr4
+ ; SAVEALL: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
+ ; SAVEALL: STW8 killed $x12, 8, $x1
+ ; SAVEALL: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEALL: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL: renamable $cr4lt = COPY $cr0gt
+ ; SAVEALL: renamable $x3 = COPY $x29
+ ; SAVEALL: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEALL: $x12 = LWZ8 8, $x1
+ ; SAVEALL: $cr2 = MTOCRF8 $x12
+ ; SAVEALL: $cr4 = MTOCRF8 killed $x12
+ ; SAVEALL: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-AIX-LABEL: name: CRAllSave
+ ; SAVEALL-AIX: liveins: $x3, $x29, $x30, $x31, $cr2, $cr4
+ ; SAVEALL-AIX: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
+ ; SAVEALL-AIX: STW8 killed $x12, 8, $x1
+ ; SAVEALL-AIX: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
+ ; SAVEALL-AIX: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
+ ; SAVEALL-AIX: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEALL-AIX: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL-AIX: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL-AIX: renamable $cr4lt = COPY $cr0gt
+ ; SAVEALL-AIX: renamable $x3 = COPY $x29
+ ; SAVEALL-AIX: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEALL-AIX: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+ ; SAVEALL-AIX: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
+ ; SAVEALL-AIX: $x12 = LWZ8 8, $x1
+ ; SAVEALL-AIX: $cr2 = MTOCRF8 $x12
+ ; SAVEALL-AIX: $cr4 = MTOCRF8 killed $x12
+ ; SAVEALL-AIX: BLR8 implicit $lr8, implicit $rm, implicit $x3
renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr2lt = COPY $cr0gt
renamable $cr4lt = COPY $cr0gt
@@ -58,6 +105,76 @@ liveins:
body: |
bb.0.entry:
liveins: $x3
+ ; SAVEONE-LABEL: name: CR2Save
+ ; SAVEONE: liveins: $x3, $x14, $cr2
+ ; SAVEONE: $x12 = MFOCRF8 killed $cr2
+ ; SAVEONE: STW8 killed $x12, 8, $x1
+ ; SAVEONE: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
+ ; SAVEONE: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEONE: renamable $cr2lt = COPY $cr0gt
+ ; SAVEONE: renamable $x3 = COPY $x14
+ ; SAVEONE: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
+ ; SAVEONE: $x12 = LWZ8 8, $x1
+ ; SAVEONE: $cr2 = MTOCRF8 killed $x12
+ ; SAVEONE: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-LABEL: name: CR2Save
+ ; SAVEALL: liveins: $x3, $x14, $cr2
+ ; SAVEALL: $x12 = MFCR8 implicit killed $cr2
+ ; SAVEALL: STW8 killed $x12, 8, $x1
+ ; SAVEALL: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
+ ; SAVEALL: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL: renamable $x3 = COPY $x14
+ ; SAVEALL: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
+ ; SAVEALL: $x12 = LWZ8 8, $x1
+ ; SAVEALL: $cr2 = MTOCRF8 killed $x12
+ ; SAVEALL: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-AIX-LABEL: name: CR2Save
+ ; SAVEALL-AIX: liveins: $x3, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31, $cr2
+ ; SAVEALL-AIX: $x12 = MFCR8 implicit killed $cr2
+ ; SAVEALL-AIX: STW8 killed $x12, 8, $x1
+ ; SAVEALL-AIX: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.17, align 16)
+ ; SAVEALL-AIX: STD killed $x15, -136, $x1 :: (store (s64) into %fixed-stack.16)
+ ; SAVEALL-AIX: STD killed $x16, -128, $x1 :: (store (s64) into %fixed-stack.15, align 16)
+ ; SAVEALL-AIX: STD killed $x17, -120, $x1 :: (store (s64) into %fixed-stack.14)
+ ; SAVEALL-AIX: STD killed $x18, -112, $x1 :: (store (s64) into %fixed-stack.13, align 16)
+ ; SAVEALL-AIX: STD killed $x19, -104, $x1 :: (store (s64) into %fixed-stack.12)
+ ; SAVEALL-AIX: STD killed $x20, -96, $x1 :: (store (s64) into %fixed-stack.11, align 16)
+ ; SAVEALL-AIX: STD killed $x21, -88, $x1 :: (store (s64) into %fixed-stack.10)
+ ; SAVEALL-AIX: STD killed $x22, -80, $x1 :: (store (s64) into %fixed-stack.9, align 16)
+ ; SAVEALL-AIX: STD killed $x23, -72, $x1 :: (store (s64) into %fixed-stack.8)
+ ; SAVEALL-AIX: STD killed $x24, -64, $x1 :: (store (s64) into %fixed-stack.7, align 16)
+ ; SAVEALL-AIX: STD killed $x25, -56, $x1 :: (store (s64) into %fixed-stack.6)
+ ; SAVEALL-AIX: STD killed $x26, -48, $x1 :: (store (s64) into %fixed-stack.5, align 16)
+ ; SAVEALL-AIX: STD killed $x27, -40, $x1 :: (store (s64) into %fixed-stack.4)
+ ; SAVEALL-AIX: STD killed $x28, -32, $x1 :: (store (s64) into %fixed-stack.3, align 16)
+ ; SAVEALL-AIX: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
+ ; SAVEALL-AIX: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
+ ; SAVEALL-AIX: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEALL-AIX: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL-AIX: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL-AIX: renamable $x3 = COPY $x14
+ ; SAVEALL-AIX: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEALL-AIX: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+ ; SAVEALL-AIX: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
+ ; SAVEALL-AIX: $x28 = LD -32, $x1 :: (load (s64) from %fixed-stack.3, align 16)
+ ; SAVEALL-AIX: $x27 = LD -40, $x1 :: (load (s64) from %fixed-stack.4)
+ ; SAVEALL-AIX: $x26 = LD -48, $x1 :: (load (s64) from %fixed-stack.5, align 16)
+ ; SAVEALL-AIX: $x25 = LD -56, $x1 :: (load (s64) from %fixed-stack.6)
+ ; SAVEALL-AIX: $x24 = LD -64, $x1 :: (load (s64) from %fixed-stack.7, align 16)
+ ; SAVEALL-AIX: $x23 = LD -72, $x1 :: (load (s64) from %fixed-stack.8)
+ ; SAVEALL-AIX: $x22 = LD -80, $x1 :: (load (s64) from %fixed-stack.9, align 16)
+ ; SAVEALL-AIX: $x21 = LD -88, $x1 :: (load (s64) from %fixed-stack.10)
+ ; SAVEALL-AIX: $x20 = LD -96, $x1 :: (load (s64) from %fixed-stack.11, align 16)
+ ; SAVEALL-AIX: $x19 = LD -104, $x1 :: (load (s64) from %fixed-stack.12)
+ ; SAVEALL-AIX: $x18 = LD -112, $x1 :: (load (s64) from %fixed-stack.13, align 16)
+ ; SAVEALL-AIX: $x17 = LD -120, $x1 :: (load (s64) from %fixed-stack.14)
+ ; SAVEALL-AIX: $x16 = LD -128, $x1 :: (load (s64) from %fixed-stack.15, align 16)
+ ; SAVEALL-AIX: $x15 = LD -136, $x1 :: (load (s64) from %fixed-stack.16)
+ ; SAVEALL-AIX: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.17, align 16)
+ ; SAVEALL-AIX: $x12 = LWZ8 8, $x1
+ ; SAVEALL-AIX: $cr2 = MTOCRF8 killed $x12
+ ; SAVEALL-AIX: BLR8 implicit $lr8, implicit $rm, implicit $x3
renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr2lt = COPY $cr0gt
renamable $x3 = COPY $x14
@@ -80,8 +197,6 @@ body: |
; ELF V2 ABI allows saving only the clobbered cr fields,
; whereas the other ABIs do not.
- ; SAVEONE: $x12 = MFOCRF8 killed $cr2
- ; SAVEALL: $x12 = MFCR8 implicit killed $cr2
; CHECK-DAG: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
; CHECK-DAG: STW8 killed $x12, 8, $x1
>From 0ed8fbe7ce50002f41e30f6952d56744ee6d433a Mon Sep 17 00:00:00 2001
From: Maryam Moghadas <maryammo at ca.ibm.com>
Date: Mon, 22 Jan 2024 10:01:20 -0500
Subject: [PATCH 2/4] Address review comments
---
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 27 +-
llvm/test/CodeGen/PowerPC/ppc64-crsave.mir | 261 +++++++++----------
2 files changed, 130 insertions(+), 158 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index dd80d7558f5c5a..f84473855edd32 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -2735,11 +2735,6 @@ bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();
}
-static bool isGPR(MCPhysReg Reg) { return Reg >= PPC::R0 && Reg <= PPC::R31; }
-static bool isG8R(MCPhysReg Reg) { return Reg >= PPC::X0 && Reg <= PPC::X31; }
-static bool isFPR(MCPhysReg Reg) { return Reg >= PPC::F0 && Reg <= PPC::F31; }
-static bool isVR(MCPhysReg Reg) { return Reg >= PPC::V0 && Reg <= PPC::V31; }
-
void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
BitVector &SavedRegs) const {
// The AIX ABI uses traceback tables for EH which require that if callee-saved
@@ -2755,7 +2750,7 @@ void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
if (SavedRegs.none())
return;
- const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
+ const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
MCPhysReg LowestGPR = PPC::R31;
MCPhysReg LowestG8R = PPC::X31;
@@ -2772,25 +2767,29 @@ void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
MCPhysReg Cand = CSRegs[i];
if (!SavedRegs.test(Cand))
continue;
- if (isGPR(Cand) && Cand < LowestGPR)
+ if (PPC::GPRCRegClass.contains(Cand) && Cand < LowestGPR)
LowestGPR = Cand;
- else if (isG8R(Cand) && Cand < LowestG8R)
+ else if (PPC::G8RCRegClass.contains(Cand) && Cand < LowestG8R)
LowestG8R = Cand;
- else if (isFPR(Cand) && Cand < LowestFPR)
+ else if ((PPC::F4RCRegClass.contains(Cand) ||
+ PPC::F8RCRegClass.contains(Cand)) &&
+ Cand < LowestFPR)
LowestFPR = Cand;
- else if (isVR(Cand) && Cand < LowestVR)
+ else if (PPC::VRRCRegClass.contains(Cand) && Cand < LowestVR)
LowestVR = Cand;
}
for (int i = 0; CSRegs[i]; i++) {
MCPhysReg Cand = CSRegs[i];
- if (isGPR(Cand) && Cand > LowestGPR)
+ if (PPC::GPRCRegClass.contains(Cand) && Cand > LowestGPR)
SavedRegs.set(Cand);
- else if (isG8R(Cand) && Cand > LowestG8R)
+ else if (PPC::G8RCRegClass.contains(Cand) && Cand > LowestG8R)
SavedRegs.set(Cand);
- else if (isFPR(Cand) && Cand > LowestFPR)
+ else if ((PPC::F4RCRegClass.contains(Cand) ||
+ PPC::F8RCRegClass.contains(Cand)) &&
+ Cand > LowestFPR)
SavedRegs.set(Cand);
- else if (isVR(Cand) && Cand > LowestVR)
+ else if (PPC::VRRCRegClass.contains(Cand) && Cand > LowestVR)
SavedRegs.set(Cand);
}
}
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
index 9d00db269e33fc..281e7f39d6874b 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -1,14 +1,14 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-altivec \
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
# RUN: FileCheck %s --check-prefixes=SAVEONE
-# RUN: llc -mtriple powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-altivec \
+# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
# RUN: FileCheck %s --check-prefixes=SAVEALL
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
# RUN: FileCheck %s --check-prefixes=SAVEALL-AIX
@@ -23,77 +23,64 @@ body: |
liveins: $x3
; SAVEONE-LABEL: name: CRAllSave
; SAVEONE: liveins: $x3, $x29, $cr2, $cr4
- ; SAVEONE: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
- ; SAVEONE: STW8 killed $x12, 8, $x1
- ; SAVEONE: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
- ; SAVEONE: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; SAVEONE: renamable $cr2lt = COPY $cr0gt
- ; SAVEONE: renamable $cr4lt = COPY $cr0gt
- ; SAVEONE: renamable $x3 = COPY $x29
- ; SAVEONE: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
- ; SAVEONE: $x12 = LWZ8 8, $x1
- ; SAVEONE: $cr2 = MTOCRF8 $x12
- ; SAVEONE: $cr4 = MTOCRF8 killed $x12
- ; SAVEONE: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEONE-NEXT: {{ $}}
+ ; SAVEONE-NEXT: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
+ ; SAVEONE-NEXT: STW8 killed $x12, 8, $x1
+ ; SAVEONE-NEXT: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEONE-NEXT: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEONE-NEXT: renamable $cr2lt = COPY $cr0gt
+ ; SAVEONE-NEXT: renamable $cr4lt = COPY $cr0gt
+ ; SAVEONE-NEXT: renamable $x3 = COPY $x29
+ ; SAVEONE-NEXT: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEONE-NEXT: $x12 = LWZ8 8, $x1
+ ; SAVEONE-NEXT: $cr2 = MTOCRF8 $x12
+ ; SAVEONE-NEXT: $cr4 = MTOCRF8 killed $x12
+ ; SAVEONE-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ;
; SAVEALL-LABEL: name: CRAllSave
; SAVEALL: liveins: $x3, $x29, $cr2, $cr4
- ; SAVEALL: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
- ; SAVEALL: STW8 killed $x12, 8, $x1
- ; SAVEALL: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
- ; SAVEALL: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; SAVEALL: renamable $cr2lt = COPY $cr0gt
- ; SAVEALL: renamable $cr4lt = COPY $cr0gt
- ; SAVEALL: renamable $x3 = COPY $x29
- ; SAVEALL: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
- ; SAVEALL: $x12 = LWZ8 8, $x1
- ; SAVEALL: $cr2 = MTOCRF8 $x12
- ; SAVEALL: $cr4 = MTOCRF8 killed $x12
- ; SAVEALL: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-NEXT: {{ $}}
+ ; SAVEALL-NEXT: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
+ ; SAVEALL-NEXT: STW8 killed $x12, 8, $x1
+ ; SAVEALL-NEXT: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEALL-NEXT: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL-NEXT: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL-NEXT: renamable $cr4lt = COPY $cr0gt
+ ; SAVEALL-NEXT: renamable $x3 = COPY $x29
+ ; SAVEALL-NEXT: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEALL-NEXT: $x12 = LWZ8 8, $x1
+ ; SAVEALL-NEXT: $cr2 = MTOCRF8 $x12
+ ; SAVEALL-NEXT: $cr4 = MTOCRF8 killed $x12
+ ; SAVEALL-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ;
; SAVEALL-AIX-LABEL: name: CRAllSave
; SAVEALL-AIX: liveins: $x3, $x29, $x30, $x31, $cr2, $cr4
- ; SAVEALL-AIX: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
- ; SAVEALL-AIX: STW8 killed $x12, 8, $x1
- ; SAVEALL-AIX: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
- ; SAVEALL-AIX: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
- ; SAVEALL-AIX: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
- ; SAVEALL-AIX: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; SAVEALL-AIX: renamable $cr2lt = COPY $cr0gt
- ; SAVEALL-AIX: renamable $cr4lt = COPY $cr0gt
- ; SAVEALL-AIX: renamable $x3 = COPY $x29
- ; SAVEALL-AIX: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
- ; SAVEALL-AIX: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
- ; SAVEALL-AIX: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
- ; SAVEALL-AIX: $x12 = LWZ8 8, $x1
- ; SAVEALL-AIX: $cr2 = MTOCRF8 $x12
- ; SAVEALL-AIX: $cr4 = MTOCRF8 killed $x12
- ; SAVEALL-AIX: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-AIX-NEXT: {{ $}}
+ ; SAVEALL-AIX-NEXT: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
+ ; SAVEALL-AIX-NEXT: STW8 killed $x12, 8, $x1
+ ; SAVEALL-AIX-NEXT: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
+ ; SAVEALL-AIX-NEXT: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEALL-AIX-NEXT: renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL-AIX-NEXT: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL-AIX-NEXT: renamable $cr4lt = COPY $cr0gt
+ ; SAVEALL-AIX-NEXT: renamable $x3 = COPY $x29
+ ; SAVEALL-AIX-NEXT: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEALL-AIX-NEXT: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+ ; SAVEALL-AIX-NEXT: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
+ ; SAVEALL-AIX-NEXT: $x12 = LWZ8 8, $x1
+ ; SAVEALL-AIX-NEXT: $cr2 = MTOCRF8 $x12
+ ; SAVEALL-AIX-NEXT: $cr4 = MTOCRF8 killed $x12
+ ; SAVEALL-AIX-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr2lt = COPY $cr0gt
renamable $cr4lt = COPY $cr0gt
renamable $x3 = COPY $x29
BLR8 implicit $lr8, implicit $rm, implicit $x3
- ; CHECK-LABEL: fixedStack:
- ; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
- ; CHECK-NEXT: callee-saved-register: '$x29', callee-saved-restored: true, debug-info-variable: '',
- ; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
- ; CHECK-NEXT: - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
- ; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
- ; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
- ; CHECK-NEXT: debug-info-location: '' }
- ; CHECK-LABEL: stack:
- ; Verify the proper live-ins have been added in the prologue.
- ; CHECK: liveins: $x3, $x29, $cr2, $cr4
- ; CHECK: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
- ; CHECK-DAG: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.0)
- ; CHECK-DAG: STW8 killed $x12, 8, $x1
- ; CHECK: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.0)
- ; CHECK: $x12 = LWZ8 8, $x1
- ; CHECK: $cr2 = MTOCRF8 $x12
- ; CHECK: $cr4 = MTOCRF8 killed $x12
...
---
@@ -107,103 +94,89 @@ body: |
liveins: $x3
; SAVEONE-LABEL: name: CR2Save
; SAVEONE: liveins: $x3, $x14, $cr2
- ; SAVEONE: $x12 = MFOCRF8 killed $cr2
- ; SAVEONE: STW8 killed $x12, 8, $x1
- ; SAVEONE: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
- ; SAVEONE: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; SAVEONE: renamable $cr2lt = COPY $cr0gt
- ; SAVEONE: renamable $x3 = COPY $x14
- ; SAVEONE: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
- ; SAVEONE: $x12 = LWZ8 8, $x1
- ; SAVEONE: $cr2 = MTOCRF8 killed $x12
- ; SAVEONE: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEONE-NEXT: {{ $}}
+ ; SAVEONE-NEXT: $x12 = MFOCRF8 killed $cr2
+ ; SAVEONE-NEXT: STW8 killed $x12, 8, $x1
+ ; SAVEONE-NEXT: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
+ ; SAVEONE-NEXT: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEONE-NEXT: renamable $cr2lt = COPY $cr0gt
+ ; SAVEONE-NEXT: renamable $x3 = COPY $x14
+ ; SAVEONE-NEXT: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
+ ; SAVEONE-NEXT: $x12 = LWZ8 8, $x1
+ ; SAVEONE-NEXT: $cr2 = MTOCRF8 killed $x12
+ ; SAVEONE-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ;
; SAVEALL-LABEL: name: CR2Save
; SAVEALL: liveins: $x3, $x14, $cr2
- ; SAVEALL: $x12 = MFCR8 implicit killed $cr2
- ; SAVEALL: STW8 killed $x12, 8, $x1
- ; SAVEALL: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
- ; SAVEALL: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; SAVEALL: renamable $cr2lt = COPY $cr0gt
- ; SAVEALL: renamable $x3 = COPY $x14
- ; SAVEALL: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
- ; SAVEALL: $x12 = LWZ8 8, $x1
- ; SAVEALL: $cr2 = MTOCRF8 killed $x12
- ; SAVEALL: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-NEXT: {{ $}}
+ ; SAVEALL-NEXT: $x12 = MFCR8 implicit killed $cr2
+ ; SAVEALL-NEXT: STW8 killed $x12, 8, $x1
+ ; SAVEALL-NEXT: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
+ ; SAVEALL-NEXT: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL-NEXT: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL-NEXT: renamable $x3 = COPY $x14
+ ; SAVEALL-NEXT: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
+ ; SAVEALL-NEXT: $x12 = LWZ8 8, $x1
+ ; SAVEALL-NEXT: $cr2 = MTOCRF8 killed $x12
+ ; SAVEALL-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ;
; SAVEALL-AIX-LABEL: name: CR2Save
; SAVEALL-AIX: liveins: $x3, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31, $cr2
- ; SAVEALL-AIX: $x12 = MFCR8 implicit killed $cr2
- ; SAVEALL-AIX: STW8 killed $x12, 8, $x1
- ; SAVEALL-AIX: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.17, align 16)
- ; SAVEALL-AIX: STD killed $x15, -136, $x1 :: (store (s64) into %fixed-stack.16)
- ; SAVEALL-AIX: STD killed $x16, -128, $x1 :: (store (s64) into %fixed-stack.15, align 16)
- ; SAVEALL-AIX: STD killed $x17, -120, $x1 :: (store (s64) into %fixed-stack.14)
- ; SAVEALL-AIX: STD killed $x18, -112, $x1 :: (store (s64) into %fixed-stack.13, align 16)
- ; SAVEALL-AIX: STD killed $x19, -104, $x1 :: (store (s64) into %fixed-stack.12)
- ; SAVEALL-AIX: STD killed $x20, -96, $x1 :: (store (s64) into %fixed-stack.11, align 16)
- ; SAVEALL-AIX: STD killed $x21, -88, $x1 :: (store (s64) into %fixed-stack.10)
- ; SAVEALL-AIX: STD killed $x22, -80, $x1 :: (store (s64) into %fixed-stack.9, align 16)
- ; SAVEALL-AIX: STD killed $x23, -72, $x1 :: (store (s64) into %fixed-stack.8)
- ; SAVEALL-AIX: STD killed $x24, -64, $x1 :: (store (s64) into %fixed-stack.7, align 16)
- ; SAVEALL-AIX: STD killed $x25, -56, $x1 :: (store (s64) into %fixed-stack.6)
- ; SAVEALL-AIX: STD killed $x26, -48, $x1 :: (store (s64) into %fixed-stack.5, align 16)
- ; SAVEALL-AIX: STD killed $x27, -40, $x1 :: (store (s64) into %fixed-stack.4)
- ; SAVEALL-AIX: STD killed $x28, -32, $x1 :: (store (s64) into %fixed-stack.3, align 16)
- ; SAVEALL-AIX: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
- ; SAVEALL-AIX: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
- ; SAVEALL-AIX: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
- ; SAVEALL-AIX: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; SAVEALL-AIX: renamable $cr2lt = COPY $cr0gt
- ; SAVEALL-AIX: renamable $x3 = COPY $x14
- ; SAVEALL-AIX: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
- ; SAVEALL-AIX: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
- ; SAVEALL-AIX: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
- ; SAVEALL-AIX: $x28 = LD -32, $x1 :: (load (s64) from %fixed-stack.3, align 16)
- ; SAVEALL-AIX: $x27 = LD -40, $x1 :: (load (s64) from %fixed-stack.4)
- ; SAVEALL-AIX: $x26 = LD -48, $x1 :: (load (s64) from %fixed-stack.5, align 16)
- ; SAVEALL-AIX: $x25 = LD -56, $x1 :: (load (s64) from %fixed-stack.6)
- ; SAVEALL-AIX: $x24 = LD -64, $x1 :: (load (s64) from %fixed-stack.7, align 16)
- ; SAVEALL-AIX: $x23 = LD -72, $x1 :: (load (s64) from %fixed-stack.8)
- ; SAVEALL-AIX: $x22 = LD -80, $x1 :: (load (s64) from %fixed-stack.9, align 16)
- ; SAVEALL-AIX: $x21 = LD -88, $x1 :: (load (s64) from %fixed-stack.10)
- ; SAVEALL-AIX: $x20 = LD -96, $x1 :: (load (s64) from %fixed-stack.11, align 16)
- ; SAVEALL-AIX: $x19 = LD -104, $x1 :: (load (s64) from %fixed-stack.12)
- ; SAVEALL-AIX: $x18 = LD -112, $x1 :: (load (s64) from %fixed-stack.13, align 16)
- ; SAVEALL-AIX: $x17 = LD -120, $x1 :: (load (s64) from %fixed-stack.14)
- ; SAVEALL-AIX: $x16 = LD -128, $x1 :: (load (s64) from %fixed-stack.15, align 16)
- ; SAVEALL-AIX: $x15 = LD -136, $x1 :: (load (s64) from %fixed-stack.16)
- ; SAVEALL-AIX: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.17, align 16)
- ; SAVEALL-AIX: $x12 = LWZ8 8, $x1
- ; SAVEALL-AIX: $cr2 = MTOCRF8 killed $x12
- ; SAVEALL-AIX: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; SAVEALL-AIX-NEXT: {{ $}}
+ ; SAVEALL-AIX-NEXT: $x12 = MFCR8 implicit killed $cr2
+ ; SAVEALL-AIX-NEXT: STW8 killed $x12, 8, $x1
+ ; SAVEALL-AIX-NEXT: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.17, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x15, -136, $x1 :: (store (s64) into %fixed-stack.16)
+ ; SAVEALL-AIX-NEXT: STD killed $x16, -128, $x1 :: (store (s64) into %fixed-stack.15, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x17, -120, $x1 :: (store (s64) into %fixed-stack.14)
+ ; SAVEALL-AIX-NEXT: STD killed $x18, -112, $x1 :: (store (s64) into %fixed-stack.13, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x19, -104, $x1 :: (store (s64) into %fixed-stack.12)
+ ; SAVEALL-AIX-NEXT: STD killed $x20, -96, $x1 :: (store (s64) into %fixed-stack.11, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x21, -88, $x1 :: (store (s64) into %fixed-stack.10)
+ ; SAVEALL-AIX-NEXT: STD killed $x22, -80, $x1 :: (store (s64) into %fixed-stack.9, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x23, -72, $x1 :: (store (s64) into %fixed-stack.8)
+ ; SAVEALL-AIX-NEXT: STD killed $x24, -64, $x1 :: (store (s64) into %fixed-stack.7, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x25, -56, $x1 :: (store (s64) into %fixed-stack.6)
+ ; SAVEALL-AIX-NEXT: STD killed $x26, -48, $x1 :: (store (s64) into %fixed-stack.5, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x27, -40, $x1 :: (store (s64) into %fixed-stack.4)
+ ; SAVEALL-AIX-NEXT: STD killed $x28, -32, $x1 :: (store (s64) into %fixed-stack.3, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x29, -24, $x1 :: (store (s64) into %fixed-stack.2)
+ ; SAVEALL-AIX-NEXT: STD killed $x30, -16, $x1 :: (store (s64) into %fixed-stack.1, align 16)
+ ; SAVEALL-AIX-NEXT: STD killed $x31, -8, $x1 :: (store (s64) into %fixed-stack.0)
+ ; SAVEALL-AIX-NEXT: renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; SAVEALL-AIX-NEXT: renamable $cr2lt = COPY $cr0gt
+ ; SAVEALL-AIX-NEXT: renamable $x3 = COPY $x14
+ ; SAVEALL-AIX-NEXT: $x31 = LD -8, $x1 :: (load (s64) from %fixed-stack.0)
+ ; SAVEALL-AIX-NEXT: $x30 = LD -16, $x1 :: (load (s64) from %fixed-stack.1, align 16)
+ ; SAVEALL-AIX-NEXT: $x29 = LD -24, $x1 :: (load (s64) from %fixed-stack.2)
+ ; SAVEALL-AIX-NEXT: $x28 = LD -32, $x1 :: (load (s64) from %fixed-stack.3, align 16)
+ ; SAVEALL-AIX-NEXT: $x27 = LD -40, $x1 :: (load (s64) from %fixed-stack.4)
+ ; SAVEALL-AIX-NEXT: $x26 = LD -48, $x1 :: (load (s64) from %fixed-stack.5, align 16)
+ ; SAVEALL-AIX-NEXT: $x25 = LD -56, $x1 :: (load (s64) from %fixed-stack.6)
+ ; SAVEALL-AIX-NEXT: $x24 = LD -64, $x1 :: (load (s64) from %fixed-stack.7, align 16)
+ ; SAVEALL-AIX-NEXT: $x23 = LD -72, $x1 :: (load (s64) from %fixed-stack.8)
+ ; SAVEALL-AIX-NEXT: $x22 = LD -80, $x1 :: (load (s64) from %fixed-stack.9, align 16)
+ ; SAVEALL-AIX-NEXT: $x21 = LD -88, $x1 :: (load (s64) from %fixed-stack.10)
+ ; SAVEALL-AIX-NEXT: $x20 = LD -96, $x1 :: (load (s64) from %fixed-stack.11, align 16)
+ ; SAVEALL-AIX-NEXT: $x19 = LD -104, $x1 :: (load (s64) from %fixed-stack.12)
+ ; SAVEALL-AIX-NEXT: $x18 = LD -112, $x1 :: (load (s64) from %fixed-stack.13, align 16)
+ ; SAVEALL-AIX-NEXT: $x17 = LD -120, $x1 :: (load (s64) from %fixed-stack.14)
+ ; SAVEALL-AIX-NEXT: $x16 = LD -128, $x1 :: (load (s64) from %fixed-stack.15, align 16)
+ ; SAVEALL-AIX-NEXT: $x15 = LD -136, $x1 :: (load (s64) from %fixed-stack.16)
+ ; SAVEALL-AIX-NEXT: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.17, align 16)
+ ; SAVEALL-AIX-NEXT: $x12 = LWZ8 8, $x1
+ ; SAVEALL-AIX-NEXT: $cr2 = MTOCRF8 killed $x12
+ ; SAVEALL-AIX-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
renamable $cr2lt = COPY $cr0gt
renamable $x3 = COPY $x14
BLR8 implicit $lr8, implicit $rm, implicit $x3
- ; CHECK-LABEL: CR2Save
- ; CHECK-LABEL: fixedStack:
- ; CHECK-NEXT: - { id: 0, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
- ; CHECK-NEXT: callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
- ; CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
- ; CHECK-NEXT: - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
- ; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
- ; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
- ; CHECK-NEXT: debug-info-location: '' }
- ; CHECK-LABEL: stack:
- ; Verify the proper live-ins have been added in the prologue.
- ; CHECK: liveins: $x3, $x14, $cr2
- ; ELF V2 ABI allows saving only the clobbered cr fields,
- ; whereas the other ABIs do not.
- ; CHECK-DAG: STD killed $x14, -144, $x1 :: (store (s64) into %fixed-stack.0, align 16)
- ; CHECK-DAG: STW8 killed $x12, 8, $x1
- ; CHECK: $x14 = LD -144, $x1 :: (load (s64) from %fixed-stack.0, align 16)
- ; CHECK: $x12 = LWZ8 8, $x1
- ; CHECK: $cr2 = MTOCRF8 killed $x12
...
>From d05fb400fadb1afdcd236ffa7cc9885baf29d0c4 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas <maryammo at ca.ibm.com>
Date: Tue, 9 Apr 2024 20:05:33 -0400
Subject: [PATCH 3/4] Address more review comments
---
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 24 +-
llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll | 15 +-
.../CodeGen/PowerPC/aix-csr-vector-extabi.ll | 2 +
llvm/test/CodeGen/PowerPC/aix-csr.ll | 1 -
.../test/CodeGen/PowerPC/aix-spills-for-eh.ll | 449 +++++++++---------
5 files changed, 245 insertions(+), 246 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index f84473855edd32..a8cb199ff1b308 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -2744,20 +2744,21 @@ void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
// for which we actually use traceback tables. If another ABI needs to be
// supported that also uses them, we can add a check such as
// Subtarget.usesTraceBackTables().
- assert(Subtarget.isAIXABI() && "function only called for AIX");
+ assert(Subtarget.isAIXABI() &&
+ "Function updateCalleeSaves should only be called for AIX.");
// If there are no callee saves then there is nothing to do.
if (SavedRegs.none())
return;
- const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
- const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
+ const MCPhysReg *CSRegs =
+ Subtarget.getRegisterInfo()->getCalleeSavedRegs(&MF);
MCPhysReg LowestGPR = PPC::R31;
MCPhysReg LowestG8R = PPC::X31;
MCPhysReg LowestFPR = PPC::F31;
MCPhysReg LowestVR = PPC::V31;
- // Traverse the CSR's twice so as not to rely on ascending ordering of
+ // Traverse the CSRs twice so as not to rely on ascending ordering of
// registers in the array. The first pass finds the lowest numbered
// register and the second pass marks all higher numbered registers
// for spilling.
@@ -2781,15 +2782,12 @@ void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
for (int i = 0; CSRegs[i]; i++) {
MCPhysReg Cand = CSRegs[i];
- if (PPC::GPRCRegClass.contains(Cand) && Cand > LowestGPR)
- SavedRegs.set(Cand);
- else if (PPC::G8RCRegClass.contains(Cand) && Cand > LowestG8R)
- SavedRegs.set(Cand);
- else if ((PPC::F4RCRegClass.contains(Cand) ||
- PPC::F8RCRegClass.contains(Cand)) &&
- Cand > LowestFPR)
- SavedRegs.set(Cand);
- else if (PPC::VRRCRegClass.contains(Cand) && Cand > LowestVR)
+ if ((PPC::GPRCRegClass.contains(Cand) && Cand > LowestGPR) ||
+ (PPC::G8RCRegClass.contains(Cand) && Cand > LowestG8R) ||
+ ((PPC::F4RCRegClass.contains(Cand) ||
+ PPC::F8RCRegClass.contains(Cand)) &&
+ Cand > LowestFPR) ||
+ (PPC::VRRCRegClass.contains(Cand) && Cand > LowestVR))
SavedRegs.set(Cand);
}
}
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
index 77a41ae1023c12..1b00b1126a7a19 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
@@ -20,7 +20,7 @@
@gS1 = external global %struct_S1, align 1
-define void @call_test_byval_mem1() #0 {
+define void @call_test_byval_mem1() {
entry:
%call = call zeroext i8 @test_byval_mem1(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, ptr byval(%struct_S1) align 1 @gS1)
ret void
@@ -43,7 +43,7 @@ entry:
; ASM64BIT: bl .test_byval_mem1
; ASM64BIT: addi 1, 1, 128
-define zeroext i8 @test_byval_mem1(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S1) align 1 %s) #0 {
+define zeroext i8 @test_byval_mem1(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S1) align 1 %s) {
entry:
%load = load i8, ptr %s, align 1
ret i8 %load
@@ -70,7 +70,7 @@ entry:
@gS256 = external global %struct_S256, align 1
-define void @call_test_byval_mem2() #0 {
+define void @call_test_byval_mem2() {
entry:
%call = call zeroext i8 @test_byval_mem2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, ptr byval(%struct_S256) align 1 @gS256)
ret void
@@ -144,7 +144,7 @@ entry:
; ASM64BIT: addi 1, 1, 368
-define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S256) align 1 %s) #0 {
+define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S256) align 1 %s) {
entry:
%gep = getelementptr inbounds %struct_S256, ptr %s, i32 0, i32 0, i32 255
%load = load i8, ptr %gep, align 1
@@ -171,7 +171,7 @@ entry:
@gS57 = external global %struct_S57, align 1
-define void @call_test_byval_mem3() #0 {
+define void @call_test_byval_mem3() {
entry:
call void @test_byval_mem3(i32 42, float 0x40091EB860000000, ptr byval(%struct_S57) align 1 @gS57)
ret void
@@ -235,7 +235,7 @@ entry:
; ASM64BIT: bl .test_byval_mem3
; ASM64BIT: addi 1, 1, 128
-define void @test_byval_mem3(i32, float, ptr byval(%struct_S57) align 1 %s) #0 {
+define void @test_byval_mem3(i32, float, ptr byval(%struct_S57) align 1 %s) {
entry:
ret void
}
@@ -387,7 +387,7 @@ entry:
; ASM64BIT: bl .test_byval_mem4
; ASM64BIT: addi 1, 1, 352
-define void @test_byval_mem4(i32, ptr byval(%struct_S31) align 1, ptr byval(%struct_S256) align 1 %s) #0 {
+define void @test_byval_mem4(i32, ptr byval(%struct_S31) align 1, ptr byval(%struct_S256) align 1 %s) {
entry:
ret void
}
@@ -441,4 +441,3 @@ entry:
; 64BIT-DAG: STD %6, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8
; 64BIT-DAG: STD %7, 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
-attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
index 24311d38daa64e..8549a1ee48e26a 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
@@ -75,6 +75,7 @@ entry:
; MIR32-DAG: STXVD2X killed $v28, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.3)
; MIR32-DAG: STXVD2X killed $v29, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
; MIR32-DAG: STXVD2X killed $v30, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
+; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
; MIR32: INLINEASM
@@ -146,6 +147,7 @@ entry:
; MIR64-DAG: STXVD2X killed $v28, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.3)
; MIR64-DAG: STXVD2X killed $v29, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.2)
; MIR64-DAG: STXVD2X killed $v30, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.1)
+; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store (s128) into %fixed-stack.0)
; MIR64: INLINEASM
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr.ll b/llvm/test/CodeGen/PowerPC/aix-csr.ll
index ac62595e68b868..1dadacf1faab78 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr.ll
@@ -558,7 +558,6 @@ define dso_local double @fprs_and_gprs(i32 signext %i) {
; MIR64: INLINEASM
; MIR64-NEXT: BL8_NOP
-
; MIR64-DAG: $f31 = LFD 392, $x1 :: (load (s64) from %fixed-stack.0)
; MIR64-DAG: $f30 = LFD 384, $x1 :: (load (s64) from %fixed-stack.1, align 16)
; MIR64-DAG: $f29 = LFD 376, $x1 :: (load (s64) from %fixed-stack.2)
diff --git a/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll b/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
index 56c9bc0c04bbac..73004e87587311 100644
--- a/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
@@ -1,68 +1,70 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs --vec-extabi \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s --check-prefix 32BIT
; RUN: llc -mcpu=pwr9 -mattr=+altivec -verify-machineinstrs --vec-extabi \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix 64BIT
- at _ZTIi = external constant i8*
+ at _ZTIi = external constant ptr
; Function Attrs: uwtable mustprogress
-define dso_local signext i32 @_Z5test2iPPKc(i32 signext %argc, i8** nocapture readnone %argv) local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define dso_local signext i32 @_Z5test2iPPKc(i32 signext %argc, ptr nocapture readnone %argv) local_unnamed_addr #0 personality ptr @__gxx_personality_v0{
; 32BIT-LABEL: _Z5test2iPPKc:
; 32BIT: # %bb.0: # %entry
-; 32BIT-NEXT: mflr 0
-; 32BIT-NEXT: stwu 1, -464(1)
-; 32BIT-NEXT: stw 0, 472(1)
-; 32BIT-NEXT: stw 30, 320(1) # 4-byte Folded Spill
-; 32BIT-NEXT: li 30, 0
-; 32BIT-NEXT: stxv 52, 64(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stxv 53, 80(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 31, 324(1) # 4-byte Folded Spill
-; 32BIT-NEXT: mr 31, 3
-; 32BIT-NEXT: stw 14, 256(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 54, 96(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 15, 260(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 55, 112(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 16, 264(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 56, 128(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 17, 268(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stw 18, 272(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 57, 144(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 19, 276(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 58, 160(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 20, 280(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 59, 176(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 21, 284(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stw 22, 288(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 60, 192(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 23, 292(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 61, 208(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 24, 296(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 62, 224(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 25, 300(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stw 26, 304(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stxv 63, 240(1) # 16-byte Folded Spill
-; 32BIT-NEXT: stw 27, 308(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stw 28, 312(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stw 29, 316(1) # 4-byte Folded Spill
-; 32BIT-NEXT: stfd 15, 328(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 16, 336(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 17, 344(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 18, 352(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 19, 360(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 20, 368(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 21, 376(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 22, 384(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 23, 392(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 24, 400(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 25, 408(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 26, 416(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
-; 32BIT-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
+; 32BIT-NEXT: mflr r0
+; 32BIT-NEXT: stwu r1, -464(r1)
+; 32BIT-NEXT: stw r0, 472(r1)
+; 32BIT-NEXT: stw r30, 320(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: li r30, 0
+; 32BIT-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r31, 324(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: mr r31, r3
+; 32BIT-NEXT: stw r14, 256(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v22, 96(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r15, 260(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v23, 112(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r16, 264(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v24, 128(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r17, 268(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw r18, 272(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v25, 144(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r19, 276(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v26, 160(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r20, 280(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v27, 176(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r21, 284(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw r22, 288(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v28, 192(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r23, 292(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v29, 208(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r24, 296(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v30, 224(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r25, 300(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw r26, 304(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stxv v31, 240(r1) # 16-byte Folded Spill
+; 32BIT-NEXT: stw r27, 308(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw r28, 312(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stw r29, 316(r1) # 4-byte Folded Spill
+; 32BIT-NEXT: stfd f15, 328(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f16, 336(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f17, 344(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f18, 352(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f19, 360(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f20, 368(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f21, 376(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f22, 384(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f23, 392(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f24, 400(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f25, 408(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f26, 416(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f27, 424(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f28, 432(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f29, 440(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f30, 448(r1) # 8-byte Folded Spill
+; 32BIT-NEXT: stfd f31, 456(r1) # 8-byte Folded Spill
; 32BIT-NEXT: #APP
; 32BIT-NEXT: nop
; 32BIT-NEXT: #NO_APP
@@ -71,122 +73,122 @@ define dso_local signext i32 @_Z5test2iPPKc(i32 signext %argc, i8** nocapture re
; 32BIT-NEXT: nop
; 32BIT-NEXT: L..tmp1:
; 32BIT-NEXT: L..BB0_1: # %return
-; 32BIT-NEXT: lxv 63, 240(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 62, 224(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 61, 208(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 60, 192(1) # 16-byte Folded Reload
-; 32BIT-NEXT: mr 3, 30
-; 32BIT-NEXT: lxv 59, 176(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 58, 160(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 57, 144(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 56, 128(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 55, 112(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 54, 96(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 53, 80(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lxv 52, 64(1) # 16-byte Folded Reload
-; 32BIT-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lwz 31, 324(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 30, 320(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 29, 316(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lwz 28, 312(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 27, 308(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 26, 304(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lfd 26, 416(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lwz 25, 300(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 24, 296(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 23, 292(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lfd 25, 408(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lwz 22, 288(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 21, 284(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 20, 280(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lfd 24, 400(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lwz 19, 276(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 18, 272(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 17, 268(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lfd 23, 392(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lwz 16, 264(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 15, 260(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lwz 14, 256(1) # 4-byte Folded Reload
-; 32BIT-NEXT: lfd 22, 384(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 21, 376(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 20, 368(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 19, 360(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 18, 352(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 17, 344(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 16, 336(1) # 8-byte Folded Reload
-; 32BIT-NEXT: lfd 15, 328(1) # 8-byte Folded Reload
-; 32BIT-NEXT: addi 1, 1, 464
-; 32BIT-NEXT: lwz 0, 8(1)
-; 32BIT-NEXT: mtlr 0
+; 32BIT-NEXT: lxv v31, 240(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v30, 224(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v29, 208(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v28, 192(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: mr r3, r30
+; 32BIT-NEXT: lxv v27, 176(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v26, 160(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v25, 144(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v24, 128(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v23, 112(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v22, 96(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v21, 80(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lxv v20, 64(r1) # 16-byte Folded Reload
+; 32BIT-NEXT: lfd f31, 456(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f30, 448(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f29, 440(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f28, 432(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz r31, 324(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r30, 320(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r29, 316(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd f27, 424(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz r28, 312(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r27, 308(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r26, 304(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd f26, 416(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz r25, 300(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r24, 296(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r23, 292(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd f25, 408(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz r22, 288(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r21, 284(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r20, 280(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd f24, 400(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz r19, 276(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r18, 272(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r17, 268(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd f23, 392(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lwz r16, 264(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r15, 260(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lwz r14, 256(r1) # 4-byte Folded Reload
+; 32BIT-NEXT: lfd f22, 384(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f21, 376(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f20, 368(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f19, 360(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f18, 352(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f17, 344(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f16, 336(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: lfd f15, 328(r1) # 8-byte Folded Reload
+; 32BIT-NEXT: addi r1, r1, 464
+; 32BIT-NEXT: lwz r0, 8(r1)
+; 32BIT-NEXT: mtlr r0
; 32BIT-NEXT: blr
; 32BIT-NEXT: L..BB0_2: # %lpad
; 32BIT-NEXT: L..tmp2:
; 32BIT-NEXT: bl .__cxa_begin_catch[PR]
; 32BIT-NEXT: nop
-; 32BIT-NEXT: lwz 3, 0(3)
-; 32BIT-NEXT: add 30, 3, 31
+; 32BIT-NEXT: lwz r3, 0(r3)
+; 32BIT-NEXT: add r30, r3, r31
; 32BIT-NEXT: bl .__cxa_end_catch[PR]
; 32BIT-NEXT: nop
; 32BIT-NEXT: b L..BB0_1
;
; 64BIT-LABEL: _Z5test2iPPKc:
; 64BIT: # %bb.0: # %entry
-; 64BIT-NEXT: mflr 0
-; 64BIT-NEXT: stdu 1, -592(1)
-; 64BIT-NEXT: std 0, 608(1)
-; 64BIT-NEXT: std 30, 440(1) # 8-byte Folded Spill
-; 64BIT-NEXT: li 30, 0
-; 64BIT-NEXT: stxv 52, 112(1) # 16-byte Folded Spill
-; 64BIT-NEXT: stxv 53, 128(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 31, 448(1) # 8-byte Folded Spill
-; 64BIT-NEXT: mr 31, 3
-; 64BIT-NEXT: std 14, 312(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 54, 144(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 15, 320(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 55, 160(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 16, 328(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 56, 176(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 17, 336(1) # 8-byte Folded Spill
-; 64BIT-NEXT: std 18, 344(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 57, 192(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 19, 352(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 58, 208(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 20, 360(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 59, 224(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 21, 368(1) # 8-byte Folded Spill
-; 64BIT-NEXT: std 22, 376(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 60, 240(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 23, 384(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 61, 256(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 24, 392(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 62, 272(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 25, 400(1) # 8-byte Folded Spill
-; 64BIT-NEXT: std 26, 408(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stxv 63, 288(1) # 16-byte Folded Spill
-; 64BIT-NEXT: std 27, 416(1) # 8-byte Folded Spill
-; 64BIT-NEXT: std 28, 424(1) # 8-byte Folded Spill
-; 64BIT-NEXT: std 29, 432(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 15, 456(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 16, 464(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 17, 472(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 18, 480(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 19, 488(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 20, 496(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 21, 504(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 22, 512(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 23, 520(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 24, 528(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 25, 536(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 26, 544(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 27, 552(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 28, 560(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 29, 568(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 30, 576(1) # 8-byte Folded Spill
-; 64BIT-NEXT: stfd 31, 584(1) # 8-byte Folded Spill
+; 64BIT-NEXT: mflr r0
+; 64BIT-NEXT: stdu r1, -592(r1)
+; 64BIT-NEXT: std r0, 608(r1)
+; 64BIT-NEXT: std r30, 440(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: li r30, 0
+; 64BIT-NEXT: stxv v20, 112(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: stxv v21, 128(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r31, 448(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: mr r31, r3
+; 64BIT-NEXT: std r14, 312(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v22, 144(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r15, 320(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v23, 160(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r16, 328(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v24, 176(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r17, 336(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: std r18, 344(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v25, 192(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r19, 352(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v26, 208(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r20, 360(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v27, 224(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r21, 368(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: std r22, 376(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v28, 240(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r23, 384(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v29, 256(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r24, 392(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v30, 272(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r25, 400(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: std r26, 408(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stxv v31, 288(r1) # 16-byte Folded Spill
+; 64BIT-NEXT: std r27, 416(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: std r28, 424(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: std r29, 432(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f15, 456(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f16, 464(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f17, 472(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f18, 480(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f19, 488(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f20, 496(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f21, 504(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f22, 512(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f23, 520(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f24, 528(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f25, 536(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f26, 544(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f27, 552(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f28, 560(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f29, 568(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f30, 576(r1) # 8-byte Folded Spill
+; 64BIT-NEXT: stfd f31, 584(r1) # 8-byte Folded Spill
; 64BIT-NEXT: #APP
; 64BIT-NEXT: nop
; 64BIT-NEXT: #NO_APP
@@ -195,64 +197,64 @@ define dso_local signext i32 @_Z5test2iPPKc(i32 signext %argc, i8** nocapture re
; 64BIT-NEXT: nop
; 64BIT-NEXT: L..tmp1:
; 64BIT-NEXT: L..BB0_1: # %return
-; 64BIT-NEXT: lxv 63, 288(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 62, 272(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 61, 256(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 60, 240(1) # 16-byte Folded Reload
-; 64BIT-NEXT: extsw 3, 30
-; 64BIT-NEXT: lxv 59, 224(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 58, 208(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 57, 192(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 56, 176(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 55, 160(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 54, 144(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 53, 128(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lxv 52, 112(1) # 16-byte Folded Reload
-; 64BIT-NEXT: lfd 31, 584(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 30, 576(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 29, 568(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 28, 560(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 31, 448(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 30, 440(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 29, 432(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 27, 552(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 28, 424(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 27, 416(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 26, 408(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 26, 544(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 25, 400(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 24, 392(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 23, 384(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 25, 536(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 22, 376(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 21, 368(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 20, 360(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 24, 528(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 19, 352(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 18, 344(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 17, 336(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 23, 520(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 16, 328(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 15, 320(1) # 8-byte Folded Reload
-; 64BIT-NEXT: ld 14, 312(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 22, 512(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 21, 504(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 20, 496(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 19, 488(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 18, 480(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 17, 472(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 16, 464(1) # 8-byte Folded Reload
-; 64BIT-NEXT: lfd 15, 456(1) # 8-byte Folded Reload
-; 64BIT-NEXT: addi 1, 1, 592
-; 64BIT-NEXT: ld 0, 16(1)
-; 64BIT-NEXT: mtlr 0
+; 64BIT-NEXT: lxv v31, 288(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v30, 272(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v29, 256(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v28, 240(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: extsw r3, r30
+; 64BIT-NEXT: lxv v27, 224(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v26, 208(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v25, 192(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v24, 176(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v23, 160(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v22, 144(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v21, 128(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lxv v20, 112(r1) # 16-byte Folded Reload
+; 64BIT-NEXT: lfd f31, 584(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f30, 576(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f29, 568(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f28, 560(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r31, 448(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r30, 440(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r29, 432(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f27, 552(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r28, 424(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r27, 416(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r26, 408(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f26, 544(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r25, 400(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r24, 392(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r23, 384(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f25, 536(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r22, 376(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r21, 368(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r20, 360(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f24, 528(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r19, 352(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r18, 344(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r17, 336(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f23, 520(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r16, 328(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r15, 320(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: ld r14, 312(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f22, 512(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f21, 504(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f20, 496(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f19, 488(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f18, 480(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f17, 472(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f16, 464(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: lfd f15, 456(r1) # 8-byte Folded Reload
+; 64BIT-NEXT: addi r1, r1, 592
+; 64BIT-NEXT: ld r0, 16(r1)
+; 64BIT-NEXT: mtlr r0
; 64BIT-NEXT: blr
; 64BIT-NEXT: L..BB0_2: # %lpad
; 64BIT-NEXT: L..tmp2:
; 64BIT-NEXT: bl .__cxa_begin_catch[PR]
; 64BIT-NEXT: nop
-; 64BIT-NEXT: lwz 3, 0(3)
-; 64BIT-NEXT: add 30, 3, 31
+; 64BIT-NEXT: lwz r3, 0(r3)
+; 64BIT-NEXT: add r30, r3, r31
; 64BIT-NEXT: bl .__cxa_end_catch[PR]
; 64BIT-NEXT: nop
; 64BIT-NEXT: b L..BB0_1
@@ -262,19 +264,18 @@ entry:
to label %return unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
- catch i8* bitcast (i8** @_ZTIi to i8*)
- %1 = extractvalue { i8*, i32 } %0, 1
- %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #3
+ %0 = landingpad { ptr, i32 }
+ catch ptr @_ZTIi
+ %1 = extractvalue { ptr, i32 } %0, 1
+ %2 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIi) #3
%matches = icmp eq i32 %1, %2
br i1 %matches, label %catch, label %eh.resume
catch: ; preds = %lpad
- %3 = extractvalue { i8*, i32 } %0, 0
- %4 = tail call i8* @__cxa_begin_catch(i8* %3) #3
- %5 = bitcast i8* %4 to i32*
- %6 = load i32, i32* %5, align 4
- %add = add nsw i32 %6, %argc
+ %3 = extractvalue { ptr, i32 } %0, 0
+ %4 = tail call ptr @__cxa_begin_catch(ptr %3) #3
+ %5 = load i32, ptr %4, align 4
+ %add = add nsw i32 %5, %argc
tail call void @__cxa_end_catch()
br label %return
@@ -283,7 +284,7 @@ return: ; preds = %entry, %catch
ret i32 %retval.0
eh.resume: ; preds = %lpad
- resume { i8*, i32 } %0
+ resume { ptr, i32 } %0
}
declare signext i32 @_Z4testi(i32 signext) local_unnamed_addr
@@ -291,9 +292,9 @@ declare signext i32 @_Z4testi(i32 signext) local_unnamed_addr
declare i32 @__gxx_personality_v0(...)
; Function Attrs: nounwind readnone
-declare i32 @llvm.eh.typeid.for(i8*)
+declare i32 @llvm.eh.typeid.for(ptr)
-declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr
+declare ptr @__cxa_begin_catch(ptr) local_unnamed_addr
declare void @__cxa_end_catch() local_unnamed_addr
>From 5655c542654212e9cfd0b81d788865cd162f1ee8 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas <maryammo at ca.ibm.com>
Date: Thu, 11 Apr 2024 19:16:45 -0400
Subject: [PATCH 4/4] Remove the unneeded nounwind attribute
---
llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll | 5 ++---
llvm/test/CodeGen/PowerPC/aix-csr-vector.ll | 7 +++----
llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll | 14 ++++++--------
4 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
index 1b00b1126a7a19..77f3abb4ba2156 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
@@ -287,7 +287,7 @@ entry:
@gS31 = external global %struct_S31, align 1
-define void @call_test_byval_mem4() #0 {
+define void @call_test_byval_mem4() {
entry:
call void @test_byval_mem4(i32 42, ptr byval(%struct_S31) align 1 @gS31, ptr byval(%struct_S256) align 1 @gS256)
ret void
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
index 8549a1ee48e26a..b99ef4904d5496 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
@@ -15,7 +15,7 @@
; RUN: FileCheck --check-prefix=ASM64 %s
-define dso_local void @vec_regs() #0 {
+define dso_local void @vec_regs() {
entry:
call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
ret void
@@ -277,7 +277,7 @@ entry:
; ASM64: blr
-define dso_local void @fprs_gprs_vecregs() #0 {
+define dso_local void @fprs_gprs_vecregs() {
call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
ret void
}
@@ -1049,4 +1049,3 @@ define dso_local void @fprs_gprs_vecregs() #0 {
; ASM64: addi 1, 1, 544
; ASM64-NEXT: blr
-attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
index cbca8918fc0554..9dc06dca3d3b45 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -14,7 +14,7 @@
; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \
; RUN: FileCheck --check-prefix=ASM64 %s
-define dso_local void @vec_regs() #0 {
+define dso_local void @vec_regs() {
entry:
call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
ret void
@@ -62,7 +62,7 @@ define dso_local void @vec_regs() #0 {
; ASM64-DAG: #NO_APP
; ASM64: blr
-define dso_local void @fprs_gprs_vecregs() #0 {
+define dso_local void @fprs_gprs_vecregs() {
call void asm sideeffect "", "~{r25},~{r28},~{r31},~{f21},~{f25},~{f31},~{v20},~{v26},~{v31}"()
ret void
}
@@ -258,7 +258,7 @@ define dso_local void @fprs_gprs_vecregs() #0 {
; ASM64: blr
-define dso_local void @all_fprs_and_vecregs() #0 {
+define dso_local void @all_fprs_and_vecregs() {
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6}~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}"()
ret void
}
@@ -293,4 +293,3 @@ define dso_local void @all_fprs_and_vecregs() #0 {
; MIR64-NOT: $v29
; MIR64-NOT: $v30
; MIR64-NOT: $v31
-attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
index 32368a79fed18e..412cb758ad602c 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
@@ -31,7 +31,7 @@
; After the prologue is set.
; DISABLE: cmpw 3, 4
; DISABLE-32: stw 0,
-; DISABLE-64: std 0,
+; DISABLE-64-AIX: std 0,
; DISABLE-NEXT: bge 0, {{.*}}[[EXIT_LABEL:BB[0-9_]+]]
;
; Store %a on the stack
@@ -57,7 +57,7 @@
; DISABLE-NEXT: blr
;
-define i32 @foo(i32 %a, i32 %b) #0 {
+define i32 @foo(i32 %a, i32 %b) {
%tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false
@@ -187,7 +187,7 @@ declare i32 @something(...)
; CHECK: %for.exit
; CHECK: mtlr {{[0-9]+}}
; CHECK: blr
-define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) #0 {
+define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
entry:
br label %for.preheader
@@ -276,7 +276,7 @@ for.end: ; preds = %for.body
; Shift second argument by one and store into returned register.
; ENABLE: slwi 3, 4, 1
; ENABLE-NEXT: blr
-define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
+define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
entry:
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader
@@ -452,7 +452,7 @@ entry:
; DISABLE-64-NEXT: ld 31, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
; DISABLE-32-NEXT: lwz 31, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
; CHECK-NEXT: blr
-define i32 @inlineAsm(i32 %cond, i32 %N) #0 {
+define i32 @inlineAsm(i32 %cond, i32 %N) {
entry:
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader
@@ -698,7 +698,7 @@ end:
; Ensure no subsequent uses of callee-save register before end of function
; CHECKXX-NOT: {{[a-z]+}} [[CSR]]
; CHECK: blr
-define signext i32 @transpose() #0 {
+define signext i32 @transpose() {
entry:
%0 = load i32, ptr getelementptr inbounds ([0 x i32], ptr @columns, i64 0, i64 1), align 4
%shl.i = shl i32 %0, 7
@@ -843,5 +843,3 @@ if.end.6:
%cmp1.7 = icmp eq i32 %18, %conv18.i
br i1 %cmp1.7, label %if.then, label %cleanup
}
-
-attributes #0 = { nounwind }
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