[llvm] [InstCombine] Fold -X / -Y -> X / Y (PR #88422)

via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 11 12:26:58 PDT 2024


https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/88422

>From add0a568ddbe3c0b37c16add9b78f7fc68861f1c Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Thu, 11 Apr 2024 13:56:36 -0400
Subject: [PATCH 1/2] [InstCombine] Pre-commit tests (NFC)

---
 llvm/test/Transforms/InstCombine/div.ll | 46 +++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll
index e8a25ff44d0296..ff46965bf584e8 100644
--- a/llvm/test/Transforms/InstCombine/div.ll
+++ b/llvm/test/Transforms/InstCombine/div.ll
@@ -1648,6 +1648,52 @@ define i32 @sdiv_mul_nsw_sub_nsw(i32 %x, i32 %y) {
   ret i32 %d
 }
 
+define i32 @sdiv_neg_divisor_known_non_min(i32 %x, i32 %z) {
+; CHECK-LABEL: @sdiv_neg_divisor_known_non_min(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[Z:%.*]], 1
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[Z1:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[OR]], [[SUB]]
+; CHECK-NEXT:    ret i32 [[DIV]]
+;
+entry:
+  %or = or i32 %x, 1
+  %sub = sub nsw i32 0, %z
+  %div = sdiv i32 %or, %sub
+  ret i32 %div
+}
+
+define i32 @double_negative_division(i32 %x, i32 %z) {
+; CHECK-LABEL: @double_negative_division(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nsw i32 0, [[Z:%.*]]
+; CHECK-NEXT:    [[DIV21:%.*]] = sdiv i32 [[X:%.*]], [[SUB1]]
+; CHECK-NEXT:    [[DIV2:%.*]] = sub nsw i32 0, [[DIV21]]
+; CHECK-NEXT:    ret i32 [[DIV2]]
+;
+entry:
+  %sub2 = sub nsw i32 0, %x
+  %sub1 = sub nsw i32 0, %z
+  %div2 = sdiv i32 %sub2, %sub1
+  ret i32 %div2
+}
+
+; Negative test
+
+define i32 @negative_divisior_only(i32 %x, i32 %z) {
+; CHECK-LABEL: @negative_divisior_only(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nsw i32 0, [[Z:%.*]]
+; CHECK-NEXT:    [[DIV2:%.*]] = sdiv i32 [[X:%.*]], [[SUB1]]
+; CHECK-NEXT:    ret i32 [[DIV2]]
+;
+entry:
+  %sub1 = sub nsw i32 0, %z
+  %div2 = sdiv i32 %x, %sub1
+  ret i32 %div2
+}
+
+
 ; exact propagates
 
 define i8 @sdiv_sdiv_mul_nsw_exact_exact(i8 %x, i8 %y, i8 %z) {

>From 1e8560f7b641ccac7ca57b00e815ee53a3987994 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Thu, 11 Apr 2024 13:58:15 -0400
Subject: [PATCH 2/2] [InstCombine] Fold -X / -Y -> X / Y, and X / -Y -> -(X /
 Y) if X is known to not be INT_MIN

Alive Proofs:

https://alive2.llvm.org/ce/z/zLMokH
https://alive2.llvm.org/ce/z/xviNg3
https://alive2.llvm.org/ce/z/4rdGvf
---
 .../InstCombine/InstCombineMulDivRem.cpp      | 26 +++++++++++++++----
 llvm/test/Transforms/InstCombine/div.ll       | 14 +++++-----
 2 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index 8c698e52b5a0e6..1d1d926de1e65c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -1572,8 +1572,7 @@ Instruction *InstCombinerImpl::visitSDiv(BinaryOperator &I) {
     // -X / C --> X / -C (if the negation doesn't overflow).
     // TODO: This could be enhanced to handle arbitrary vector constants by
     //       checking if all elements are not the min-signed-val.
-    if (!Op1C->isMinSignedValue() &&
-        match(Op0, m_NSWSub(m_Zero(), m_Value(X)))) {
+    if (!Op1C->isMinSignedValue() && match(Op0, m_NSWNeg(m_Value(X)))) {
       Constant *NegC = ConstantInt::get(Ty, -(*Op1C));
       Instruction *BO = BinaryOperator::CreateSDiv(X, NegC);
       BO->setIsExact(I.isExact());
@@ -1581,12 +1580,30 @@ Instruction *InstCombinerImpl::visitSDiv(BinaryOperator &I) {
     }
   }
 
-  // -X / Y --> -(X / Y)
+  KnownBits KnownDividend = computeKnownBits(Op0, 0, &I);
+  KnownBits KnownDivisor = computeKnownBits(Op1, 0, &I);
   Value *Y;
-  if (match(&I, m_SDiv(m_OneUse(m_NSWSub(m_Zero(), m_Value(X))), m_Value(Y))))
+  // -X / -Y --> (X / Y)
+  if (!KnownDividend.getSignedMinValue().isMinSignedValue() &&
+      !KnownDivisor.getSignedMinValue().isMinSignedValue() &&
+      match(&I, m_SDiv(m_NSWNeg(m_Value(X)), m_NSWNeg(m_Value(Y))))) {
+    auto *NewDiv = BinaryOperator::CreateSDiv(X, Y);
+    NewDiv->setIsExact(I.isExact());
+    return NewDiv;
+  }
+
+  // -X / Y --> -(X / Y)
+  if (match(&I, m_SDiv(m_OneUse(m_NSWNeg(m_Value(X))), m_Value(Y))))
     return BinaryOperator::CreateNSWNeg(
         Builder.CreateSDiv(X, Y, I.getName(), I.isExact()));
 
+  // X / -Y --> -(X / Y), if X is known to not be INT_MIN
+  if (!KnownDivisor.getSignedMinValue().isMinSignedValue() &&
+      match(&I, m_SDiv(m_Value(X), m_OneUse(m_NSWNeg(m_Value(Y)))))) {
+    return BinaryOperator::CreateNSWNeg(
+        Builder.CreateSDiv(X, Y, I.getName(), I.isExact()));
+  }
+
   // abs(X) / X --> X > -1 ? 1 : -1
   // X / abs(X) --> X > -1 ? 1 : -1
   if (match(&I, m_c_BinOp(
@@ -1597,7 +1614,6 @@ Instruction *InstCombinerImpl::visitSDiv(BinaryOperator &I) {
                               ConstantInt::getAllOnesValue(Ty));
   }
 
-  KnownBits KnownDividend = computeKnownBits(Op0, 0, &I);
   if (!I.isExact() &&
       (match(Op1, m_Power2(Op1C)) || match(Op1, m_NegatedPower2(Op1C))) &&
       KnownDividend.countMinTrailingZeros() >= Op1C->countr_zero()) {
diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll
index ff46965bf584e8..3975300817f0ed 100644
--- a/llvm/test/Transforms/InstCombine/div.ll
+++ b/llvm/test/Transforms/InstCombine/div.ll
@@ -1651,10 +1651,10 @@ define i32 @sdiv_mul_nsw_sub_nsw(i32 %x, i32 %y) {
 define i32 @sdiv_neg_divisor_known_non_min(i32 %x, i32 %z) {
 ; CHECK-LABEL: @sdiv_neg_divisor_known_non_min(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[Z:%.*]], 1
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[Z1:%.*]]
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[OR]], [[SUB]]
-; CHECK-NEXT:    ret i32 [[DIV]]
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[DIV:%.*]] = sub nsw i32 0, [[DIV1:%.*]]
+; CHECK-NEXT:    [[DIV2:%.*]] = sdiv i32 [[OR]], [[DIV]]
+; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
 entry:
   %or = or i32 %x, 1
@@ -1683,9 +1683,9 @@ entry:
 define i32 @negative_divisior_only(i32 %x, i32 %z) {
 ; CHECK-LABEL: @negative_divisior_only(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[SUB1:%.*]] = sub nsw i32 0, [[Z:%.*]]
-; CHECK-NEXT:    [[DIV2:%.*]] = sdiv i32 [[X:%.*]], [[SUB1]]
-; CHECK-NEXT:    ret i32 [[DIV2]]
+; CHECK-NEXT:    [[DIV2:%.*]] = sub nsw i32 0, [[DIV21:%.*]]
+; CHECK-NEXT:    [[DIV3:%.*]] = sdiv i32 [[X:%.*]], [[DIV2]]
+; CHECK-NEXT:    ret i32 [[DIV3]]
 ;
 entry:
   %sub1 = sub nsw i32 0, %z



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