[llvm] [SelectionDAG] Propogate Disjoint flag. (PR #88370)

[via llvm-commits]

https://github.com/fengfeng09 updated https://github.com/llvm/llvm-project/pull/88370

>From 1b9f288d54329ab9fab973f994b7ed66dacb895e Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 00:29:12 +0800
Subject: [PATCH 1/2] Precommit test for propogate disjoint.NFC

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 .../X86/propogate-disjoint-in-shl-or.ll       | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll

diff --git a/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
new file mode 100644
index 00000000000000..794cd8492500ab
--- /dev/null
+++ b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=x86_64 %s -start-before=x86-isel -o - -stop-after=x86-isel | FileCheck %s
+
+define void @add_shl_or_disjoint(i32 %x, ptr addrspace(1) %o) {
+  ; CHECK-LABEL: name: add_shl_or_disjoint
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $edi, $rsi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edi
+  ; CHECK-NEXT:   [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY1]], 2, implicit-def dead $eflags
+  ; CHECK-NEXT:   [[OR32ri:%[0-9]+]]:gr32 = OR32ri [[SHL32ri]], -1069531068, implicit-def dead $eflags
+  ; CHECK-NEXT:   [[ADD32ri:%[0-9]+]]:gr32 = ADD32ri [[OR32ri]], 1234567890, implicit-def dead $eflags
+  ; CHECK-NEXT:   MOV32mr [[COPY]], 1, $noreg, 0, $noreg, killed [[ADD32ri]] :: (store (s32) into %ir.o, addrspace 1)
+  ; CHECK-NEXT:   RET 0
+  %or = or disjoint i32 %x, 4027584529
+  %shl = shl i32 %or, 2
+  %add = add i32 %shl, 1234567890
+  store i32 %add, ptr addrspace(1) %o
+  ret void
+}
+

>From 1f57f3d438cb9a6f651d7f0d1e1663d382f6e655 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Fri, 12 Apr 2024 00:32:59 +0800
Subject: [PATCH 2/2] [SelectionDAG] Propogate Disjoint flag.

Signed-off-by: feng.feng <feng.feng at iluvatar.com>
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp         | 2 ++
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp      | 2 ++
 llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll | 8 ++++----
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8fe074666a3dc9..59ef66fba73164 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9530,6 +9530,8 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) {
   SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT);
   SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC);
   SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1);
+  // Propogate flags.
+  SelectionDAG::FlagInserter FlagsInserter(DAG, LogicOp->getFlags());
   return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2);
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 409d66adfd67d1..dd5c3d741aa7dc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -544,6 +544,8 @@ bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
     if (!C.isSubsetOf(DemandedBits)) {
       EVT VT = Op.getValueType();
       SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT);
+      // Propogate flags.
+      SelectionDAG::FlagInserter FlagsInserter(TLO.DAG, Op->getFlags());
       SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
       return TLO.CombineTo(Op, NewOp);
     }
diff --git a/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
index 794cd8492500ab..3eebf04311a76d 100644
--- a/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
+++ b/llvm/test/CodeGen/X86/propogate-disjoint-in-shl-or.ll
@@ -8,10 +8,10 @@ define void @add_shl_or_disjoint(i32 %x, ptr addrspace(1) %o) {
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edi
-  ; CHECK-NEXT:   [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY1]], 2, implicit-def dead $eflags
-  ; CHECK-NEXT:   [[OR32ri:%[0-9]+]]:gr32 = OR32ri [[SHL32ri]], -1069531068, implicit-def dead $eflags
-  ; CHECK-NEXT:   [[ADD32ri:%[0-9]+]]:gr32 = ADD32ri [[OR32ri]], 1234567890, implicit-def dead $eflags
-  ; CHECK-NEXT:   MOV32mr [[COPY]], 1, $noreg, 0, $noreg, killed [[ADD32ri]] :: (store (s32) into %ir.o, addrspace 1)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:gr64_nosp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32bit
+  ; CHECK-NEXT:   [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r $noreg, 4, killed [[INSERT_SUBREG]], 165036822, $noreg
+  ; CHECK-NEXT:   MOV32mr [[COPY]], 1, $noreg, 0, $noreg, killed [[LEA64_32r]] :: (store (s32) into %ir.o, addrspace 1)
   ; CHECK-NEXT:   RET 0
   %or = or disjoint i32 %x, 4027584529
   %shl = shl i32 %or, 2