[llvm] ff74236 - [VectorCombine] foldShuffleOfCastops - ensure we add all new instructions onto the worklist

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-04-11T15:47:09+01:00
New Revision: ff74236f342c7bc185f56a07bab7bd0cf356c7c6

URL: https://github.com/llvm/llvm-project/commit/ff74236f342c7bc185f56a07bab7bd0cf356c7c6
DIFF: https://github.com/llvm/llvm-project/commit/ff74236f342c7bc185f56a07bab7bd0cf356c7c6.diff

LOG: [VectorCombine] foldShuffleOfCastops - ensure we add all new instructions onto the worklist

When creating cast(shuffle(x,y)) we were only adding the cast() to the worklist, not the new shuffle, preventing recursive combines.

foldShuffleOfBinops is also failing to do this, but I still need to add test coverage for this.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/VectorCombine.cpp
    llvm/test/Transforms/VectorCombine/X86/pr67803.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 658e8e74fe5b80..44cba60013afa3 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1440,6 +1440,8 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) {
     NewInst->copyIRFlags(B0);
     NewInst->andIRFlags(B1);
   }
+
+  // TODO: Add Shuf0/Shuf1 to WorkList?
   replaceValue(I, *NewBO);
   return true;
 }
@@ -1533,6 +1535,7 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) {
     NewInst->andIRFlags(C1);
   }
 
+  Worklist.pushValue(Shuf);
   replaceValue(I, *Cast);
   return true;
 }

diff  --git a/llvm/test/Transforms/VectorCombine/X86/pr67803.ll b/llvm/test/Transforms/VectorCombine/X86/pr67803.ll
index da94bf7f0c907f..69fd6f6a10e2a6 100644
--- a/llvm/test/Transforms/VectorCombine/X86/pr67803.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/pr67803.ll
@@ -8,9 +8,8 @@ define <4 x i64> @PR67803(<8 x i32> %x, <8 x i32> %y, <8 x float> %a, <8 x float
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <8 x i32> [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[CMP_LO:%.*]] = shufflevector <8 x i1> [[CMP]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; CHECK-NEXT:    [[CMP_HI:%.*]] = shufflevector <8 x i1> [[CMP]], <8 x i1> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT:    [[SEXT_LO:%.*]] = sext <4 x i1> [[CMP_LO]] to <4 x i32>
-; CHECK-NEXT:    [[SEXT_HI:%.*]] = sext <4 x i1> [[CMP_HI]] to <4 x i32>
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[SEXT_LO]], <4 x i32> [[SEXT_HI]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <4 x i1> [[CMP_LO]], <4 x i1> [[CMP_HI]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    [[TMP1:%.*]] = sext <8 x i1> [[TMP0]] to <8 x i32>
 ; CHECK-NEXT:    [[CONCAT:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64>
 ; CHECK-NEXT:    [[MASK:%.*]] = bitcast <4 x i64> [[CONCAT]] to <8 x float>
 ; CHECK-NEXT:    [[SEL:%.*]] = tail call noundef <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x float> [[MASK]])