[llvm] [TableGen] New tblgen Instruction bit to disable DAGISel pattern imports (PR #88382)
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Thu Apr 11 05:14:31 PDT 2024
https://github.com/jofrn created https://github.com/llvm/llvm-project/pull/88382
Added a new DAGISelShouldIgnore property to class Instruction in Target.td, similar to FastISelShouldIgnore. This allows one to avoid a record's DAGISel .td implementation and .inc generation.
>From f4e7c49aebeed2d253049d86943c36681c17f84c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 11 Apr 2024 01:15:36 -0400
Subject: [PATCH] [TableGen] New tblgen Instruction bit to disable DAGISel
pattern imports
Added a new DAGISelShouldIgnore property to class Instruction in Target.td, similar to FastISelShouldIgnore. This allows one to avoid a record's DAGISel .td implementation and .inc generation.
---
llvm/include/llvm/Target/Target.td | 4 ++++
llvm/utils/TableGen/Common/CodeGenInstruction.cpp | 1 +
llvm/utils/TableGen/Common/CodeGenInstruction.h | 1 +
llvm/utils/TableGen/DAGISelEmitter.cpp | 15 ++++++++++++++-
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 1f7dc6922f13e4..61dc04595b62b9 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -777,6 +777,10 @@ class Instruction : InstructionEncoding {
/// SelectionDAG can.
bit FastISelShouldIgnore = false;
+ /// Should DAGISel ignore this instruction. In cases where lowering may
+ /// be done elsewhere or is unneeded, DAGISel may skip over them.
+ bit DAGISelShouldIgnore = false;
+
/// HasPositionOrder: Indicate tablegen to sort the instructions by record
/// ID, so that instruction that is defined earlier can be sorted earlier
/// in the assembly matching table.
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index 18a4e7b0f18b23..a76efb76bfc319 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -465,6 +465,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isConvergent = R->getValueAsBit("isConvergent");
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
+ DAGISelShouldIgnore = R->getValueAsBit("DAGISelShouldIgnore");
variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
isAuthenticated = R->getValueAsBit("isAuthenticated");
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index b658259b4892ee..c36bfba245f66b 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -282,6 +282,7 @@ class CodeGenInstruction {
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
bool FastISelShouldIgnore : 1;
+ bool DAGISelShouldIgnore : 1;
bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index b43a8e659dd9c5..4fbeafdc2355fb 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -165,8 +165,21 @@ void DAGISelEmitter::run(raw_ostream &OS) {
// Add all the patterns to a temporary list so we can sort them.
Records.startTimer("Sort patterns");
std::vector<const PatternToMatch *> Patterns;
- for (const PatternToMatch &PTM : CGP.ptms())
+ for (const PatternToMatch &PTM : CGP.ptms()) {
+
+ // Disable import of patterns marked as ignore.
+ const TreePatternNode &Dst = PTM.getDstPattern();
+ if (!Dst.isLeaf()) {
+ const Record *Op = Dst.getOperator();
+ const bool shouldIgnore =
+ Op->isSubClassOf("Instruction") &&
+ CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
+ if (shouldIgnore)
+ continue;
+ }
+
Patterns.push_back(&PTM);
+ }
// We want to process the matches in order of minimal cost. Sort the patterns
// so the least cost one is at the start.
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